发明申请
- 专利标题: MEMORY/LOGIC CONJUGATE SYSTEM
- 专利标题(中): 内存/逻辑连接系统
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申请号: US12977243申请日: 2010-12-23
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公开(公告)号: US20110255323A1公开(公告)日: 2011-10-20
- 发明人: Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
- 申请人: Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
- 优先权: JP2008-173905 20080702
- 主分类号: G11C5/06
- IPC分类号: G11C5/06
摘要:
There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
公开/授权文献
- US08305789B2 Memory/logic conjugate system 公开/授权日:2012-11-06