发明申请
US20110278655A1 Semiconductor Device with Circuit for Reduced Parasitic Inductance
审中-公开
具有降低寄生电感的电路的半导体器件
- 专利标题： Semiconductor Device with Circuit for Reduced Parasitic Inductance
- 专利标题（中）： 具有降低寄生电感的电路的半导体器件
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申请号： US13192584申请日： 2011-07-28
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公开(公告)号： US20110278655A1公开(公告)日： 2011-11-17
- 发明人: Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
- 申请人： Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
- 申请人地址： JP Kanagawa
- 专利权人： Renesas Electronics Corporation
- 当前专利权人： Renesas Electronics Corporation
- 当前专利权人地址： JP Kanagawa
- 优先权： JP2006-149489 20060530
- 主分类号： H01L27/06
- IPC分类号： H01L27/06
摘要：
Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
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