发明申请
US20120018730A1 STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES
有权
非平面半导体器件中应力锁定的结构和方法
- 专利标题: STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES
- 专利标题(中): 非平面半导体器件中应力锁定的结构和方法
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申请号: US12841408申请日: 2010-07-22
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公开(公告)号: US20120018730A1公开(公告)日: 2012-01-26
- 发明人: Sivananda K. Kanakasabapathy , Hemanth Jagannathan , Sanjay Mehta
- 申请人: Sivananda K. Kanakasabapathy , Hemanth Jagannathan , Sanjay Mehta
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: H01L29/786
- IPC分类号: H01L29/786 ; H01L21/336
摘要:
Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.
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