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    Replacement gate electrode with multi-thickness conductive metallic nitride layers
    1.
    发明授权
    Replacement gate electrode with multi-thickness conductive metallic nitride layers 有权
    具有多层导电金属氮化物层的替代栅电极

    公开(公告)号：US09202698B2

    公开(公告)日：2015-12-01

    申请号：US13406784

    申请日：2012-02-28

    申请人： Hemanth Jagannathan ,  Vamsi K. Paruchuri

    发明人： Hemanth Jagannathan ,  Vamsi K. Paruchuri

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L23/485 ,  H01L29/51 ,  H01L21/84

    CPC分类号： H01L21/28229 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/485 ,  H01L27/092 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.

    摘要翻译： 可以通过在替代栅极方案中提供具有不同厚度的导电金属氮化物层来提供具有不同功函数的栅电极。 在去除一次性栅极结构和形成栅极电介质层时，至少一个增量厚度的导电金属氮化物层被添加到一些栅极空腔内，而不被添加到一些其它栅极腔中。 随后添加最小厚度的导电金属氮化物层作为连续层。 如此形成的导电金属氮化物层在不同的栅腔上具有不同的厚度。 沉积栅极填充导电材料层，并执行平面化以提供具有不同导电金属氮化物层厚度的多个栅电极。 导电金属氮化物层的不同厚度可以提供具有约400mV范围的不同功函数。

    ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION
    3.
    发明申请
    ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION 审中-公开
    用于替换门槛整合的耐蚀阻挡层

    公开(公告)号：US20130309856A1

    公开(公告)日：2013-11-21

    申请号：US13471980

    申请日：2012-05-15

    申请人： HEMANTH JAGANNATHAN ,  SANJAY MEHTA ,  CHUN-CHEN YEH

    发明人： HEMANTH JAGANNATHAN ,  SANJAY MEHTA ,  CHUN-CHEN YEH

    IPC分类号： H01L21/28

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/785

    摘要： Semiconductor devices and methods of their fabrication are disclosed. One method includes forming a semiconductor device structure including a plurality of dummy gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the dummy gates. An etch resistant nitride layer is applied above the dielectric gap filling material to maintain the aspect ratio of the gap filling material. In addition, the dummy gates are removed by implementing an etching process. Further, replacement gates are formed in regions of the device structure previously occupied by the dummy gates.

    摘要翻译： 公开了半导体器件及其制造方法。 一种方法包括形成包括多个伪栅极的半导体器件结构和具有在伪栅极之间的预定宽高比的介质间隙填充材料。 将耐蚀刻氮化物层施加在电介质间隙填充材料上方以保持间隙填充材料的纵横比。 此外，通过实施蚀刻工艺来去除伪栅极。 此外，替换栅极形成在先前由虚拟栅极占据的器件结构的区域中。

    LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS
    5.
    发明申请
    LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS 审中-公开

    公开(公告)号：US20130214358A1

    公开(公告)日：2013-08-22

    申请号：US13399040

    申请日：2012-02-17

    申请人： Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy

    发明人： Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/42384 ,  H01L29/4908

    摘要： A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.

    Low resistance source and drain extensions for ETSOI
    6.
    发明授权
    Low resistance source and drain extensions for ETSOI 失效

    公开(公告)号：US08486778B2

    公开(公告)日：2013-07-16

    申请号：US13183666

    申请日：2011-07-15

    申请人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    发明人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/6653 ,  H01L29/78621

    摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

    Structure and method to integrate embedded DRAM with finfet
    7.
    发明授权
    Structure and method to integrate embedded DRAM with finfet 有权
    嵌入式DRAM与finfet的结构和方法

    公开(公告)号：US08421139B2

    公开(公告)日：2013-04-16

    申请号：US12755487

    申请日：2010-04-07

    申请人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Geng Wang

    发明人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Geng Wang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/10826 ,  H01L21/26586 ,  H01L21/845 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1211

    摘要： A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.

    摘要翻译： 晶体管包括第一鳍结构和形成在衬底上的至少第二鳍结构。 在第一和第二翅片结构之间形成深沟槽区域。 深沟槽区域延伸穿过衬底的绝缘体层和衬底的半导体层。 在深沟槽区域内形成高k金属栅极。 在与金属层相邻的深沟槽区域内形成多晶硅层。 多晶硅层和高k金属层凹陷在绝缘体层的顶表面下方。 深沟槽区域中的多晶带形成在高k金属栅极和多晶硅材料的顶部上。 该多晶带的尺寸被设计成在第一和第二鳍结构的顶表面下方。 第一翅片结构和第二翅片结构电耦合到多晶带。

    FinFET device having reduce capacitance, access resistance, and contact resistance
    10.
    发明申请
    FinFET device having reduce capacitance, access resistance, and contact resistance 有权
    FinFET器件具有降低电容，访问电阻和接触电阻

    公开(公告)号：US20120193713A1

    公开(公告)日：2012-08-02

    申请号：US13017966

    申请日：2011-01-31

    申请人： Pranita Kulkarni ,  Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam Shahidi ,  Hemanth Jagannathan

    发明人： Pranita Kulkarni ,  Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam Shahidi ,  Hemanth Jagannathan

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/66803 ,  H01L29/41791 ,  H01L29/785

    摘要： A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.

    摘要翻译： 形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。 提供掩埋氧化物，鳍状物，栅极和第一间隔物。 该鳍被掺杂以形成在栅极下方延伸的延伸结。 第二间隔件形成在延伸接头的顶部。 每个是与栅极的任一侧相邻的第一间隔件之间的第二间隔件。 延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。 空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。 在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。