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    Method to improve wet etch budget in FEOL integration
    1.
    发明授权
    Method to improve wet etch budget in FEOL integration 失效
    在FEOL集成中改善湿法蚀刻预算的方法

    公开(公告)号：US08679941B2

    公开(公告)日：2014-03-25

    申请号：US13422138

    申请日：2012-03-16

    申请人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229

    摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

    ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION
    3.
    发明申请
    ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION 审中-公开
    用于替换门槛整合的耐蚀阻挡层

    公开(公告)号：US20130307079A1

    公开(公告)日：2013-11-21

    申请号：US13494511

    申请日：2012-06-12

    申请人： HEMANTH JAGANNATHAN ,  SANJAY MEHTA ,  CHUN-CHEN YEH

    发明人： HEMANTH JAGANNATHAN ,  SANJAY MEHTA ,  CHUN-CHEN YEH

    IPC分类号： H01L29/78

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/785

    摘要： Semiconductor devices and methods of their fabrication are disclosed. One device includes a plurality of gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the gates. The device further includes an etch resistant nitride layer that is configured to maintain the aspect ratio of the dielectric gap filling material during fabrication of the device and is disposed above the dielectric gap filling material and between the plurality of gates.

    摘要翻译： 公开了半导体器件及其制造方法。 一个装置包括多个栅极和具有在门之间的预定宽高比的电介质间隙填充材料。 该器件还包括耐蚀刻氮化物层，其被配置为在器件的制造过程中保持电介质间隙填充材料的纵横比并且设置在电介质间隙填充材料之上和多个栅极之间。

    DIVOT-FREE PLANARIZATION DIELECTRIC LAYER FOR REPLACEMENT GATE
    4.
    发明申请
    DIVOT-FREE PLANARIZATION DIELECTRIC LAYER FOR REPLACEMENT GATE 审中-公开

    公开(公告)号：US20130292746A1

    公开(公告)日：2013-11-07

    申请号：US13606706

    申请日：2012-09-07

    申请人： Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L29/78

    CPC分类号： F04B19/006 ,  F04B43/0054 ,  F04B43/043 ,  F04B45/047

    摘要： After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.

    Structure and method for stress latching in non-planar semiconductor devices
    6.
    发明授权
    Structure and method for stress latching in non-planar semiconductor devices 有权
    非平面半导体器件中应力锁定的结构和方法

    公开(公告)号：US08394684B2

    公开(公告)日：2013-03-12

    申请号：US12841408

    申请日：2010-07-22

    申请人： Sivananda K. Kanakasabapathy ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Sivananda K. Kanakasabapathy ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L21/84

    CPC分类号： H01L27/0886 ,  H01L21/82 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785

    摘要： Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.

    摘要翻译： 公开了一种技术来将外部应力施加到源极/漏极半导体鳍状物侧壁区域上并将其锁定到半导体鳍片上，然后释放侧壁以用于随后的盐化和接触形成。 特别地，本公开提供了一种方法，其中半导体的选定部分经受非晶化离子注入，其相对于在栅极堆叠下面的半导体鳍片的部分使半导体鳍片的选定部分的晶体结构脱落， 用各种衬垫封装。 形成至少一个应力衬垫，然后通过进行应力闭锁退火而发生应力记忆。 在该退火期间，发生错位取向的晶体结构的再结晶。 去除至少一个应力衬垫，然后执行源极/漏极区域中的半导体鳍片的合并。

    METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION
    8.
    发明申请
    METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 失效
    提高生产费用总额的方法

    公开(公告)号：US20120178236A1

    公开(公告)日：2012-07-12

    申请号：US13422138

    申请日：2012-03-16

    申请人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229

    摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

    Predicting rare events using principal component analysis and partial least squares
    10.
    发明申请
    Predicting rare events using principal component analysis and partial least squares 审中-公开
    使用主成分分析和偏最小二乘预测罕见事件

    公开(公告)号：US20100076785A1

    公开(公告)日：2010-03-25

    申请号：US12284929

    申请日：2008-09-25

    申请人： Sanjay Mehta ,  Debashis Neogi

    发明人： Sanjay Mehta ,  Debashis Neogi

    IPC分类号： G06Q50/00 ,  G06F17/30

    CPC分类号： G06Q50/24 ,  G06F19/328 ,  G06N20/00 ,  G06Q50/22 ,  G16H50/20 ,  G16H50/50 ,  Y02A90/22 ,  Y02A90/26

    摘要： Systems and methods are provided for predicting rare events, such as hospitalization events. Data related to health and/or healthcare may be compiled from a number of sources and used to construct a predictive model. The predictive model employ Principal Component Analysis (PCA) and Partial Least Squares (PLS). The data may be arranged in a timeline, and formatted in such a way as to provide discrete temporal “batches”. This arrangement may facilitate the PCA and PLS decomposition of the data into predictive models. These models may then be applied to an individual's data, to create a prediction of healthcare related events.

    摘要翻译： 提供系统和方法来预测罕见事件，如住院事件。 与健康和/或保健有关的数据可以从许多来源编制并用于构建预测模型。 预测模型采用主成分分析（PCA）和偏最小二乘法（PLS）。 数据可以以时间线布置，并且以提供离散时间“批次”的方式进行格式化。 这种安排可以促进PCA和PLS将数据分解成预测模型。 然后可以将这些模型应用于个人的数据，以创建与医疗相关事件的预测。