Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers

Invention Application

US20120074567A1 Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers 有权

Title translation: 导电层非线性部分之间形成垂直互连结构的半导体器件和方法

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Patent Title: Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers
Patent Title (中): 导电层非线性部分之间形成垂直互连结构的半导体器件和方法
Application No.: US13312852

Application Date: 2011-12-06
Publication No.: US20120074567A1

Publication Date: 2012-03-29
Inventor: Zigmund R. Camacho , Dioscoro A. Merilo , Jairus L. Pisigan , Frederick R. Dahilig
Applicant: Zigmund R. Camacho , Dioscoro A. Merilo , Jairus L. Pisigan , Frederick R. Dahilig
Applicant Address: SG Singapore
Assignee: STATS ChipPAC, Ltd.
Current Assignee: STATS ChipPAC, Ltd.
Current Assignee Address: SG Singapore
Main IPC: H01L23/498
IPC: H01L23/498 ; H01L23/48

Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers

Abstract:

A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.

Abstract(Chinese):

半导体器件通过在具有圆形凹槽的第一临时载体上形成第一导电层而制成。第一导电层由于圆形的凹陷而具有非线性部分。在第一导电层的非线性部分上形成凸块。半导体管芯安装在载体上。第二导电层形成在具有圆形凹槽的第二临时载体上。第二导电层由于圆形凹陷而具有非线性部分。第二载体安装在凸块上。在第一半导体管芯周围的第一和第二临时载体之间沉积密封剂。去除第一和第二载体以留下第一和第二导电层。通过第一导电层和密封剂形成导电通孔以电连接到第一半导体管芯上的接触焊盘。

Public/Granted literature

US08890328B2 Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers Public/Granted day:2014-11-18

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L23/00	半导体或其他固态器件的零部件（H01L25/00优先）
H01L23/48	.用于向或自处于工作中的固态物体通电的装置，例如引线或接线端装置
H01L23/488	..由焊接或黏结结构组成
H01L23/498	...引线位于绝缘衬底上的