发明申请
US20120080802A1 THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE
审中-公开
通过在具有降低的PARASITIC电容的N +外延波形中通过硅
- 专利标题: THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE
- 专利标题(中): 通过在具有降低的PARASITIC电容的N +外延波形中通过硅
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申请号: US12894218申请日: 2010-09-30
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公开(公告)号: US20120080802A1公开(公告)日: 2012-04-05
- 发明人: Kangguo Cheng , Subramanian Iyer , Ali Khakifirooz , Pranita Kulkarni
- 申请人: Kangguo Cheng , Subramanian Iyer , Ali Khakifirooz , Pranita Kulkarni
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 主分类号: H01L23/522
- IPC分类号: H01L23/522 ; H01L21/768
摘要:
A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
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