Provided is a pipeline circuit capable of flexibly controlling clock frequencies regardless of whether a pipeline operation by a flow control is stopped or not, without significantly increasing a processing latency even if a clock frequency is decreased, and in response to performance requests for a processing throughput. Among P clocks (P is a positive integer), the phases of which are delayed in the order from a first clock to a P-th clock, for example, among six clocks of P0 to P5, two successive clocks, the phases of which are delayed from each other by a predetermined phase, are allocated to a plurality of stages, for example, five-stage pipeline buffers 32a to 32e, in the order from a previous stage to a subsequent stage, and also are allocated so that one clock signal having an identical phase is shared between two adjacent pipeline buffers.