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公开(公告)号：US08862647B2
公开(公告)日：2014-10-14
申请号：US13262748
申请日：2011-04-12
申请人： Atsufumi Shibayama
发明人： Atsufumi Shibayama
CPC分类号： H03M7/24 , G06F7/49915 , G06F7/49942
摘要： Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit calculates the exponent of the plurality of data. Included is a bit string generator that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator that calculates the exponent of the plurality of data based on bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data.
摘要翻译： 提供了一种半导体集成电路和指数计算方法，当通过公共指数对多个数据进行归一化时，加速指数计算并减小电路规模和功耗。 当通过公共指数对多个数据进行归一化时，半导体集成电路计算多个数据的指数。 包括位串生成器，其生成包含具有指示相邻位的值不同的转移值的位的第二位串，或者指示相邻位的值对于第一位的每对相邻位没有不同的非转移值 构成数据的位串，以及指数运算部，其基于从构成多个数据的多个第一比特串生成的多个第二比特串的转换值的比特位置，计算多个数据的指数。
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公开(公告)号：US06950908B2
公开(公告)日：2005-09-27
申请号：US10191401
申请日：2002-07-10
CPC分类号： G06F12/0815
摘要： The processors #0 to #3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor #1 that executes a thread updates the self-cache memory #1, if the data of the same address exists in the cache memory #2 of the processor #2 that executes a child thread, it updates the cache memory #2 simultaneously, but even if it exists in the cache memory #0 of the processor #0 that executes a parent thread, it doesn't rewrite the cache memory #0 but only records that rewriting has been performed in the cache memory #1. When the processor #0 completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread.
摘要翻译： 处理器＃0到＃3并行地执行执行顺序的多个线程。 当执行线程的处理器＃1更新自缓存存储器＃1时，如果在执行子线程的处理器＃2的高速缓存存储器＃2中存在相同地址的数据，则其更新高速缓存存储器＃2 同时，即使存在执行母线程的处理器＃0的高速缓存存储器＃0中，也不会重写高速缓存存储器＃0，而仅记录在高速缓冲存储器＃1中进行了重写。当 处理器＃0完成线程，具有从子线程重写的数据的高速缓存行可能是无效的，并且没有这样的记录的高速缓存行被判断为有效。 在执行下一个线程期间是否检查可能无效的高速缓存行真正无效或有效。
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公开(公告)号：US08576967B2
公开(公告)日：2013-11-05
申请号：US12737195
申请日：2009-04-14
申请人： Atsufumi Shibayama
发明人： Atsufumi Shibayama
IPC分类号： H04L7/00
摘要： It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit. The communication timing control circuit generates the communication timing signal determined by a frequency ratio information and a phase relation information, the frequency ratio information setting a frequency ratio of the first clock signal to the second clock signal, the phase relation information indicating a phase relation between the first clock signal and the second clock signal.
摘要翻译： 可以提供高度可靠的半导体器件和通信方法，其中可以在具有可在每个电路中设置的时钟频率的大自由度的电路之间进行通信，决定性操作和小的通信等待时间 。 根据本发明的半导体器件包括：第一电路，其执行基于第一时钟信号的处理，所述第一时钟信号具有与第二时钟信号的频率（N为正整数）的M / N倍的频率， M是大于N的正整数）; 基于所述第二时钟信号执行处理的第二电路; 以及通信定时控制电路，其生成通信定时信号，以控制第一电路与第二电路进行通信的定时。 通信定时控制电路生成由频率比信息和相位关系信息确定的通信定时信号，频率比信息设定第一时钟信号与第二时钟信号的频率比，表示相位关系的相位关系信息 第一时钟信号和第二时钟信号。
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公开(公告)号：US08242814B2
公开(公告)日：2012-08-14
申请号：US11575168
申请日：2005-09-16
申请人： Koichi Nose , Masayuki Mizuno , Atsufumi Shibayama
发明人： Koichi Nose , Masayuki Mizuno , Atsufumi Shibayama
IPC分类号： H03B19/00
CPC分类号： H03K5/00006 , G06F1/06 , H03K5/13 , H03K5/1565 , H03K2005/00052 , H03L7/07 , H03L7/0814
摘要： A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.
摘要翻译： 时钟转换电路（1）接收并将具有1 /（f×m）相位差的频率f的m相时钟转换为相位差为1 /（f×m）的频率f的n相时钟 n）。 单相时钟发生电路（2）接收具有1 /（f×n）的相位差当量时间的频率f的n相时钟，以产生与相位差等效时间的上升沿或下降沿同步的单相时钟 n相时钟。 由于输入到时钟转换电路（1）的m相时钟的频率为'f'，所以如果确定了单相时钟的期望频率，那么可以从以下等式获得“n”：频率 单相时钟等于（f×n）。 该值“n”被设置为时钟转换电路（1），从而从频率f的m相时钟获得频率f的n相时钟，以提供期望频率的单相时钟。
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公开(公告)号：US20120098583A1
公开(公告)日：2012-04-26
申请号：US13380006
申请日：2010-04-28
申请人： Atsufumi Shibayama
发明人： Atsufumi Shibayama
IPC分类号： H03H11/26
CPC分类号： G06F1/06 , G06F9/3869
摘要： Provided is a pipeline circuit capable of flexibly controlling clock frequencies regardless of whether a pipeline operation by a flow control is stopped or not, without significantly increasing a processing latency even if a clock frequency is decreased, and in response to performance requests for a processing throughput. Among P clocks (P is a positive integer), the phases of which are delayed in the order from a first clock to a P-th clock, for example, among six clocks of P0 to P5, two successive clocks, the phases of which are delayed from each other by a predetermined phase, are allocated to a plurality of stages, for example, five-stage pipeline buffers 32a to 32e, in the order from a previous stage to a subsequent stage, and also are allocated so that one clock signal having an identical phase is shared between two adjacent pipeline buffers.
摘要翻译： 提供一种能够灵活地控制时钟频率的流水线电路，而不管流量控制的流水线操作是否停止，而即使时钟频率降低也不会显着增加处理等待时间，并且响应于对处理吞吐量的性能请求 。 在P个时钟（P为正整数）中，其相位按照从第一时钟到第P时钟的顺序延迟，例如在P0至P5的六个时钟之间，两个连续的时钟，其相位相位 以预定相位彼此延迟，以从前一级到后级的顺序分配给多级，例如五级流水线缓冲器32a至32e，并且还被分配为使得一个时钟 具有相同相位的信号在两个相邻流水线缓冲器之间共享。
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6.发明授权Clock signal frequency dividing circuit and clock signal frequency dividing method 有权时钟信号分频电路和时钟信号分频方式公开(公告)号：US08081017B2
公开(公告)日：2011-12-20
申请号：US12515901
申请日：2007-11-09
申请人： Atsufumi Shibayama , Koichi Nose
发明人： Atsufumi Shibayama , Koichi Nose
IPC分类号： H03K21/00
CPC分类号： H03K23/48 , G06F1/08 , H03K23/667
摘要： To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and M are integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.
摘要翻译： 为了提供一种合理的分频电路，其中分频时钟信号的周期时间的变化小，在分频时钟信号和测试成本的最小周期时间很少的场合很多。 其分频比被指定为N / M的时钟信号分频电路都是N和M都是整数，包括选择三种情况之一的输出时钟选择电路（200）：输出输入时钟信号 输入时钟信号被反相输出，不输出输入时钟信号; 以及时钟选择控制电路（100），其产生用于控制输出时钟选择电路的上述选择的控制信号。 时钟选择控制电路在输入时钟信号的每个周期控制输出时钟选择电路的上述选择。
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公开(公告)号：US20110089981A1
公开(公告)日：2011-04-21
申请号：US12737195
申请日：2009-04-14
申请人： Atsufumi Shibayama
发明人： Atsufumi Shibayama
IPC分类号： H04L7/00
摘要： It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit. The communication timing control circuit generates the communication timing signal determined by a frequency ratio information and a phase relation information, the frequency ratio information setting a frequency ratio of the first clock signal to the second clock signal, the phase relation information indicating a phase relation between the first clock signal and the second clock signal.
摘要翻译： 可以提供高度可靠的半导体器件和通信方法，其中可以在具有可在每个电路中设置的时钟频率的大自由度的电路之间进行通信，决定性操作和小的通信等待时间 。 根据本发明的半导体器件包括：第一电路，其执行基于第一时钟信号的处理，所述第一时钟信号具有与第二时钟信号的频率（N为正整数）的M / N倍的频率， M是大于N的正整数）; 基于所述第二时钟信号执行处理的第二电路; 以及通信定时控制电路，其生成通信定时信号，以控制第一电路与第二电路进行通信的定时。 通信定时控制电路生成由频率比信息和相位关系信息确定的通信定时信号，频率比信息设定第一时钟信号与第二时钟信号的频率比，表示相位关系的相位关系信息 第一时钟信号和第二时钟信号。
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8.发明授权Program parallelization device, program parallelization method, and program parallelization program 有权程序并行化设备，程序并行化方法和程序并行程序公开(公告)号：US07533375B2
公开(公告)日：2009-05-12
申请号：US10811925
申请日：2004-03-30
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A control/data flow analysis unit analyzes the control flow and the data flow of a sequential processing program, and a fork point candidate determination unit determines fork point candidates taking this as the reference. A best fork point candidate combination determination unit determines the best fork point candidate combination by taking as the reference the result from the evaluation of the parallel execution performance of a test fork point candidate combination by a parallel execution performance evaluation unit, and a parallelized program output unit generates and outputs a parallelized program by inserting a fork command based on the best fork point candidate combination.
摘要翻译： 控制/数据流分析单元分析顺序处理程序的控制流程和数据流，叉点候选确定单元确定将其作为参考的叉点候选。 最佳叉点候选组合确定单元通过并行执行性能评估单元的并行执行性能评估单元的并行执行性能的评估的结果作为基准，来确定最佳叉点候选组合，并行程序输出 单元通过基于最佳叉点候选组合插入fork命令来生成并输出并行化程序。
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9.发明授权Data dependency detection using history table of entry number hashed from memory address 有权使用从存储器地址散列的入口号历史表的数据相关性检测公开(公告)号：US07418583B2
公开(公告)日：2008-08-26
申请号：US11126310
申请日：2005-05-11
IPC分类号： G06F9/34
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3842
摘要： A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.
摘要翻译： 检测器检测由至少一个处理器执行的指令之间的地址中的至少一种依赖性，所述检测器被用于检测存在所述至少一种依赖性的可能性，其中如果存在所述至少一种依赖性 事实上，检测器检测到存在至少一种依赖性的可能性，并且如果实际上不存在至少一种依赖性，则检测器可以检测至少一种类型的伪随机 依赖。 检测器具有具有多个条目的执行历史存储单元和用于将存储器访问指令的地址转换为条目号的地址转换器，其中不同的地址可以被转换为相同的条目号。
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公开(公告)号：US07082601B2
公开(公告)日：2006-07-25
申请号：US10196613
申请日：2002-07-17
IPC分类号： G06F9/45
CPC分类号： G06F9/4806 , G06F9/3842 , G06F9/3851
摘要： In a parallel processor system for executing a plurality of threads in parallel to each other by a plurality of thread execution units, the respective thread execution units allow for forking of a slave thread from an individual thread execution unit into another arbitrary thread execution unit. The respective thread execution units are managed in three states, a free state where fork is possible, a busy state where a thread is being executed, and a term state where a thread being terminated and yet to be settled exists. At the time of forking of a new thread, when there exists no thread execution unit at the free state, a thread that the thread execution unit at the term state has is merged into its immediately succeeding slave thread to bring the thread execution unit in question to the free state and conduct forking of a new thread.
摘要翻译： 在用于通过多个线程执行单元彼此并行地执行多个线程的并行处理器系统中，各个线程执行单元允许将从线程从单独的线程执行单元分支到另一个任意线程执行单元。 相应的线程执行单元以三种状态进行管理，其中fork是可用的空闲状态，正在执行线程的忙状态以及线程被终止且尚待结算的项状态。 在分配新线程时，如果在空闲状态下不存在线程执行单元，那么术语状态下的线程执行单元的线程被合并到其紧随的从线程中，从而使线程执行单元出现问题 到自由状态，并进行划线新线程。
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