A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.