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6 条记录 (耗时 0.021 秒)

    Test method for screening local bit-line defects in a memory array
    1.
    发明授权
    Test method for screening local bit-line defects in a memory array 有权
    用于筛选存储器阵列中局部位线缺陷的测试方法

    公开(公告)号：US08498168B2

    公开(公告)日：2013-07-30

    申请号：US13085942

    申请日：2011-04-13

    申请人： Yin Chin Huang ,  Chu Pang Huang ,  Yi Fang Chang ,  Cheng Chi Liu ,  Chang Chan Yang ,  Min Kuang Lee

    发明人： Yin Chin Huang ,  Chu Pang Huang ,  Yi Fang Chang ,  Cheng Chi Liu ,  Chang Chan Yang ,  Min Kuang Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C29/025 ,  G11C2029/1204

    摘要： A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.

    摘要翻译： 检测存储器阵列上的制造缺陷的方法可以包括利用测试电路来将存储器阵列的位线上的所选择的电压提供为漏极偏置，其中存储器阵列被配置为使用第一电压作为读取的漏极偏置 并且选择的电压高于第一电压，并且响应于提供所选择的电压作为漏极偏置来确定指示存储器阵列的位线和另一个部件之间的制造缺陷的泄漏电流是否存在。 还提供了相应的测试装置。

    Parallel threshold voltage margin search for MLC memory application
    2.
    发明授权
    Parallel threshold voltage margin search for MLC memory application 有权
    并行阈值电压裕度搜索MLC存储器应用

    公开(公告)号：US07580302B2

    公开(公告)日：2009-08-25

    申请号：US11551974

    申请日：2006-10-23

    申请人： Wen Chiao Ho ,  Chin Hung Chang ,  Cheng-Chi Liu ,  Kuen-Long Chang ,  Chun Hsiung Hung

    发明人： Wen Chiao Ho ,  Chin Hung Chang ,  Cheng-Chi Liu ,  Kuen-Long Chang ,  Chun Hsiung Hung

    IPC分类号： G11C29/00

    CPC分类号： G11C29/50 ,  G11C11/5642 ,  G11C16/04 ,  G11C29/50004 ,  G11C2211/5634 ,  G11C2211/5644

    摘要： A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.

    摘要翻译： 用于确定存储器阵列中的读取电压余量的方法将从存储器阵列读取的数据产生的读取和编码与从加载数据生成的预期总和进行比较。 读取电压（Vt）是步进的，将读取的和码与预期的和码进行比较，以确定提供匹配和码的Vt范围。 当Vt跨过其范围时，以并行方式确定多个读取电压余量（即，MLC存储器阵列的多个编程电平之间的读取电压余量）。

    SYSTEM AND METHOD FOR TESTING FOR DEFECTS IN A SEMICONDUCTOR MEMORY ARRAY
    4.
    发明申请
    SYSTEM AND METHOD FOR TESTING FOR DEFECTS IN A SEMICONDUCTOR MEMORY ARRAY 有权
    用于测试半导体存储器阵列中的缺陷的系统和方法

    公开(公告)号：US20120127797A1

    公开(公告)日：2012-05-24

    申请号：US12953213

    申请日：2010-11-23

    申请人： Yin Chin Huang ,  Chu Pang Huang ,  Cheng Chi Liu ,  Min Kuang Li ,  Chang Chan Yang ,  Yi Fang Chang

    发明人： Yin Chin Huang ,  Chu Pang Huang ,  Cheng Chi Liu ,  Min Kuang Li ,  Chang Chan Yang ,  Yi Fang Chang

    IPC分类号： G11C29/44 ,  G11C16/26 ,  G11C16/04

    CPC分类号： G11C29/50016 ,  G11C11/401

    摘要： A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.

    摘要翻译： 用于测试半导体存储器件的系统和方法包括输入到存储器单元控制栅极的可变电压。 可以将控制栅极的电压从用于正常存储器单元操作（诸如读取操作）的电压电平变化到可用于检测存储器件中的缺陷的电压电平。 在测试期间，施加到控制栅极的电压电平低于施加到存储器单元的诸如漏极端子的第二端子的电压电平。 在一些实施例中，对于缺陷的测试可以包括将负电压施加到控制栅极，同时将正电压施加到漏极端子，这可以揭示栅极 - 漏极泄漏缺陷的存在。

    System and method for testing for defects in a semiconductor memory array
    5.
    发明授权
    System and method for testing for defects in a semiconductor memory array 有权
    用于测试半导体存储器阵列中的缺陷的系统和方法

    公开(公告)号：US08605525B2

    公开(公告)日：2013-12-10

    申请号：US12953213

    申请日：2010-11-23

    申请人： Yin Chin Huang ,  Chu Pang Huang ,  Cheng Chi Liu ,  Min Kuang Li ,  Chang Chan Yang ,  Yi Fang Chang

    发明人： Yin Chin Huang ,  Chu Pang Huang ,  Cheng Chi Liu ,  Min Kuang Li ,  Chang Chan Yang ,  Yi Fang Chang

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50016 ,  G11C11/401

    摘要： A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.

    摘要翻译： 用于测试半导体存储器件的系统和方法包括输入到存储器单元控制栅极的可变电压。 可以将控制栅极的电压从用于正常存储器单元操作（诸如读取操作）的电压电平变化到可用于检测存储器件中的缺陷的电压电平。 在测试期间，施加到控制栅极的电压电平低于施加到存储器单元的诸如漏极端子的第二端子的电压电平。 在一些实施例中，对于缺陷的测试可以包括将负电压施加到控制栅极，同时将正电压施加到漏极端子，这可以揭示栅极 - 漏极泄漏缺陷的存在。

    TEST METHOD FOR SCREENING LOCAL BIT-LINE DEFECTS IN A MEMORY ARRAY
    6.
    发明申请
    TEST METHOD FOR SCREENING LOCAL BIT-LINE DEFECTS IN A MEMORY ARRAY 有权
    用于在存储器阵列中屏蔽局部位线缺陷的测试方法

    公开(公告)号：US20120263002A1

    公开(公告)日：2012-10-18

    申请号：US13085942

    申请日：2011-04-13

    申请人： Yin Chin Huang ,  Chu Pang Huang ,  Yi Fang Chang ,  Cheng Chi Liu ,  Chang Chan Yang ,  Min Kuang Lee

    发明人： Yin Chin Huang ,  Chu Pang Huang ,  Yi Fang Chang ,  Cheng Chi Liu ,  Chang Chan Yang ,  Min Kuang Lee

    IPC分类号： G11C29/04

    CPC分类号： G11C29/025 ,  G11C2029/1204

    摘要： A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.

    摘要翻译： 检测存储器阵列上的制造缺陷的方法可以包括利用测试电路来将存储器阵列的位线上的所选择的电压提供为漏极偏置，其中存储器阵列被配置为使用第一电压作为读取的漏极偏置 并且选择的电压高于第一电压，并且响应于提供所选择的电压作为漏极偏置来确定指示存储器阵列的位线和另一个部件之间的制造缺陷的泄漏电流是否存在。 还提供了相应的测试装置。