Invention Application
US20120168904A1 Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System
有权
包括立方体或四边形系统的绝缘层的半导体器件
- Patent Title: Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System
- Patent Title (中): 包括立方体或四边形系统的绝缘层的半导体器件
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Application No.: US13418472Application Date: 2012-03-13
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Publication No.: US20120168904A1Publication Date: 2012-07-05
- Inventor: Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
- Applicant: Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
- Priority: KR10-2007-0098402 20070928; KR10-2008-0083516 20080826
- Main IPC: H01L29/92
- IPC: H01L29/92
Abstract:
Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
Public/Granted literature
- US08710564B2 Semiconductor device including insulating layer of cubic system or tetragonal system Public/Granted day:2014-04-29
Information query
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