发明申请
- 专利标题： METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETERMINING AN OPTIMAL POWER STATE OF THE APPARATUS BASED ON RESIDENCY TIME OF NON-CORE DOMAINS IN A POWER SAVING STATE
- 专利标题（中）： 方法，装置和能源节约系统，包括根据节电状态下非核心域的居住时间确定装置的最佳电源状态
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申请号： US13311475申请日： 2011-12-05
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公开(公告)号： US20120173904A1公开(公告)日： 2012-07-05
- 发明人: Sanjeev S. Jahagirdhar , Ryan Wells , Inder Sodhi
- 申请人： Sanjeev S. Jahagirdhar , Ryan Wells , Inder Sodhi
- 主分类号： G06F1/32
- IPC分类号： G06F1/32
摘要：
A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.
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