公开(公告)号：US08972763B2

公开(公告)日：2015-03-03

申请号：US13311475

申请日：2011-12-05

申请人： Sanjeev S. Jahagirdhar ,  Ryan Wells ,  Inder Sodhi

发明人： Sanjeev S. Jahagirdhar ,  Ryan Wells ,  Inder Sodhi

IPC分类号： G06F1/32

CPC分类号： G06F1/3293 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F13/24 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

摘要翻译： 处理器可以确定驻留在省电状态的非核心域的实际驻留时间，并且基于处理器可以确定处理器的最佳省电状态（P状态）的实际驻留时间。 响应于非核心域进入省电状态，中断发生器（IG）可以产生第一中断，并且设备驱动器或操作系统可以使用第一中断来启动定时器（第一值）。 响应于退出省电状态的非核心域，IG可以产生第二中断，并且设备驱动器或操作系统可以使用第二中断来停止定时器（最终值）。 电源管理单元可以使用最终和第一个值来确定实际的驻留时间。

公开(公告)号：US20120173904A1

公开(公告)日：2012-07-05

申请号：US13311475

申请日：2011-12-05

申请人： Sanjeev S. Jahagirdhar ,  Ryan Wells ,  Inder Sodhi

发明人： Sanjeev S. Jahagirdhar ,  Ryan Wells ,  Inder Sodhi

IPC分类号： G06F1/32

CPC分类号： G06F1/3293 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F13/24 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

摘要翻译： 处理器可以确定驻留在省电状态的非核心域的实际驻留时间，并且基于处理器可以确定处理器的最佳省电状态（P状态）的实际驻留时间。 响应于非核心域进入省电状态，中断发生器（IG）可以产生第一中断，并且设备驱动器或操作系统可以使用第一中断来启动定时器（第一值）。 响应于退出省电状态的非核心域，IG可以产生第二中断，并且设备驱动器或操作系统可以使用第二中断来停止定时器（最终值）。 电源管理单元可以使用最终和第一个值来确定实际的驻留时间。

公开(公告)号：US20140325247A1

公开(公告)日：2014-10-30

申请号：US13870195

申请日：2013-04-25

申请人： Inder Sodhi ,  Sanjeev Jahagirdar ,  Ryan Wells ,  Zeev Offen ,  Shalini Sharma ,  Ken Drottar

发明人： Inder Sodhi ,  Sanjeev Jahagirdar ,  Ryan Wells ,  Zeev Offen ,  Shalini Sharma ,  Ken Drottar

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/32 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

摘要： In an embodiment, a processor includes a core to execute instructions, an agent to perform an operation independently of the core, a fabric to couple the core and agent and including a plurality of domains and a logic to receive isochronous parameter information from the agent and environmental information of a platform and to generate first and second values, and a power controller to control a frequency of the domains based at least in part on the first and second values. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括执行指令的核心，独立于核心执行操作的代理，耦合核心和代理的结构，并且包括多个域以及从代理接收等时参数信息的逻辑，以及 平台的环境信息并产生第一和第二值，以及功率控制器，至少部分地基于第一和第二值来控制域的频率。 描述和要求保护其他实施例。

公开(公告)号：US09345912B2

公开(公告)日：2016-05-24

申请号：US14066275

申请日：2013-10-29

申请人： Ryan Wells

发明人： Ryan Wells

IPC分类号： A62B3/00 ,  A62C8/00

CPC分类号： A62B3/005 ,  Y10T29/49826

摘要： The present invention provides a multi-use firefighting tool. The tool may be used as a stand-alone tool or as a supplement to existing tools. An additional aspect of the present invention is to provide a multi-use tool configured to enable, among other things, forcible entry and valve opening/closing. Further, the tool may be used to supplement a firefighting Halligan tool.

摘要翻译： 本发明提供一种多功能消防工具。 该工具可用作独立工具或作为现有工具的补充。 本发明的另一方面是提供一种多用途工具，该多用途工具被构造成能够强制进入和开启/关闭阀门。 此外，该工具可用于补充消防的哈利根工具。

公开(公告)号：US20130179705A1

公开(公告)日：2013-07-11

申请号：US13782539

申请日：2013-03-01

申请人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessmann ,  Ryan Wells ,  Nadav Shulman

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessmann ,  Ryan Wells ,  Nadav Shulman

IPC分类号： G06F1/26

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

公开(公告)号：US08832478B2

公开(公告)日：2014-09-09

申请号：US13282896

申请日：2011-10-27

申请人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessman ,  Ryan Wells

发明人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessman ,  Ryan Wells

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有多个域的处理器，至少包括对于操作系统（OS）是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来，处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外，可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。

公开(公告)号：US20130179709A1

公开(公告)日：2013-07-11

申请号：US13782578

申请日：2013-03-01

申请人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Wiessmann ,  Ryan Wells

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Wiessmann ,  Ryan Wells

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/26 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3243 ,  G06F13/14 ,  Y02D10/126

摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于确定多域处理器的非核心域不以非核域所请求的频率操作的方法，将来自非核心域的请求发送到功率 控制器降低多域处理器核心域的频率，并响应请求，降低核心域频率。 描述和要求保护其他实施例。

公开(公告)号：US20130111236A1

公开(公告)日：2013-05-02

申请号：US13282947

申请日：2011-10-27

申请人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Wiessman ,  Ryan Wells

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Wiessman ,  Ryan Wells

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/26 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3243 ,  G06F13/14 ,  Y02D10/126

摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

公开(公告)号：US20130111226A1

公开(公告)日：2013-05-02

申请号：US13285414

申请日：2011-10-31

申请人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessman ,  Ryan Wells ,  Nadav Shulman

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessman ,  Ryan Wells ,  Nadav Shulman

IPC分类号： G06F1/00

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

公开(公告)号：US20130111120A1

公开(公告)日：2013-05-02

申请号：US13282896

申请日：2011-10-27

申请人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessman ,  Ryan Wells

发明人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessman ,  Ryan Wells

IPC分类号： G06F12/08 ,  G06F12/02 ,  G06F9/54

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有多个域的处理器，至少包括对于操作系统（OS）是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来，处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外，可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。