发明申请
- 专利标题: WAFER CHIP SCALE PACKAGE CONNECTION SCHEME
- 专利标题(中): WAFER CHIP SCALE包装连接方案
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申请号: US13033064申请日: 2011-02-23
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公开(公告)号: US20120211884A1公开(公告)日: 2012-08-23
- 发明人: Frank Stepniak , Christopher Daniel Manack , Licheng M. Han
- 申请人: Frank Stepniak , Christopher Daniel Manack , Licheng M. Han
- 主分类号: H01L23/485
- IPC分类号: H01L23/485 ; H01L21/441
摘要:
A method and structure for forming a semiconductor device, for example a device including a wafer chip scale package (WCSP), can include the formation of at least one conductive layer which contacts a bond pad. The at least one conductive layer can be patterned using a first mask, then a passivation layer can be formed over the patterned at least one conductive layer. The passivation layer can be patterned using a second mask to expose the at least one conductive layer, then a conductive layer such as a solder ball, conductive bump, metal-filled paste, or another conductor is formed on the at least one conductive layer. The method can result in a structure which is formed using a reduced number of mask steps.
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