发明申请
- 专利标题: REDUCING DEFECT RATE DURING DEPOSITION OF A CHANNEL SEMICONDUCTOR ALLOY INTO AN IN SITU RECESSED ACTIVE REGION
- 专利标题(中): 在通道半导体合金沉积在现场的有源区域中减少缺陷率
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申请号: US13421394申请日: 2012-03-15
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公开(公告)号: US20120235249A1公开(公告)日: 2012-09-20
- 发明人: Stephan-Detlef Kronholz , Peter Javorka , Maciej Wiatr
- 申请人: Stephan-Detlef Kronholz , Peter Javorka , Maciej Wiatr
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人地址: KY Grand Cayman
- 优先权: DE102011005639.4 20110316
- 主分类号: H01L29/78
- IPC分类号: H01L29/78 ; H01L21/336
摘要:
When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
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