公开(公告)号：US08836047B2

公开(公告)日：2014-09-16

申请号：US13421394

申请日：2012-03-15

Applicant: Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L27/04 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.

Abstract translation: 当基于阈值电压调节半导体合金形成复杂的高k金属栅电极结构时，可以应用高效的原位工艺技术，以便在专用有源区域中形成凹槽并用半导体合金再填充凹槽。 为了在活性区域的凹陷期间减少或避免蚀刻相关的不规则性，可以控制在先前处理期间，特别是在形成沟槽隔离区域期间的铝污染程度。

公开(公告)号：US08536009B2

公开(公告)日：2013-09-17

申请号：US13197239

申请日：2011-08-03

Applicant: Peter Javorka ,  Maciej Wiatr ,  Stephan-Detlef Kronholz

Inventor： Peter Javorka ,  Maciej Wiatr ,  Stephan-Detlef Kronholz

IPC: H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/82385

Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.

Abstract translation: 在复杂的半导体器件中，可以在早期制造阶段提供高k金属栅极电极结构，其中P沟道晶体管的阈值电压调节可以基于阈值电压调节半导体合金（诸如硅/锗） 合金，用于长沟道器件，而在硅/锗合金的选择性外延生长期间可能会掩蔽短沟道器件。 在一些说明性实施例中，阈值电压调整可以在没有用于P沟道晶体管的任何晕圈注入工艺的情况下完成，而阈值电压可以通过N沟道晶体管的晕圈注入来调节。

公开(公告)号：US20120153401A1

公开(公告)日：2012-06-21

申请号：US13197239

申请日：2011-08-03

Applicant: Peter JAVORKA ,  Maciej WIATR ,  Stephan-Detlef KRONHOLZ

Inventor： Peter JAVORKA ,  Maciej WIATR ,  Stephan-Detlef KRONHOLZ

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/82385

Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.

Abstract translation: 在复杂的半导体器件中，可以在早期制造阶段提供高k金属栅极电极结构，其中P沟道晶体管的阈值电压调节可以基于阈值电压调节半导体合金（诸如硅/锗） 合金，用于长沟道器件，而在硅/锗合金的选择性外延生长期间可能会掩蔽短沟道器件。 在一些说明性实施例中，阈值电压调整可以在没有用于P沟道晶体管的任何晕圈注入工艺的情况下完成，而阈值电压可以通过N沟道晶体管的晕圈注入来调节。

公开(公告)号：US08674458B2

公开(公告)日：2014-03-18

申请号：US13483630

申请日：2012-05-30

Applicant: Stephan-Detlef Kronholz ,  Rohit Pal ,  Gunda Beernink

Inventor： Stephan-Detlef Kronholz ,  Rohit Pal ,  Gunda Beernink

IPC: H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.

Abstract translation: 当形成具有复杂的高k金属栅电极结构的晶体管和应变诱导半导体合金的复杂半导体器件时，可以通过在选择性外延生长工艺期间提供优异的生长条件来增强晶体管的均匀性和性能。 为此，可以在隔离区域保留半导体材料，以避免突出的肩部的形成。 此外，在一些说明性实施例中，为了避免不适当的材料损失，例如在去除电介质盖材料等时，实施附加机构。

公开(公告)号：US08481381B2

公开(公告)日：2013-07-09

申请号：US13232711

申请日：2011-09-14

Applicant: Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L22/10 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/7848 ,  Y02P80/30

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract translation: 在基于晶体管的基础上在半导体器件中形成高k金属栅极电极结构时，可以避免在N沟道晶体管的栅电极结构的端部处敏感材料的过度曝光，例如，在 在将应变诱导半导体材料并入P沟道晶体管的有源区域中，从而有助于提高预定晶体管特性和性能的产量。

公开(公告)号：US08377786B2

公开(公告)日：2013-02-19

申请号：US13020369

申请日：2011-02-03

Applicant: Stephan-Detlef Kronholz ,  Peter Javorka ,  Roman Boschke

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Roman Boschke

IPC: H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/31155 ,  H01L21/31111 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864

Abstract: Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.

Abstract translation: 提供了制造半导体器件的方法的实施例。 该方法包括在包括第一栅电极结构和第二栅电极结构的半导体区上形成间隔物层。 将碳引入围绕第一栅电极结构或第二栅电极结构覆盖半导体区的层的一部分。 蚀刻该层以围绕第一栅极电极结构形成第一侧壁隔离物，并围绕第二栅电极结构形成第二侧壁隔离物。

公开(公告)号：US20130040430A1

公开(公告)日：2013-02-14

申请号：US13552722

申请日：2012-07-19

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  Y02P80/30

Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

Abstract translation: 本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。 为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。 以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。

公开(公告)号：US20120235249A1

公开(公告)日：2012-09-20

申请号：US13421394

申请日：2012-03-15

Applicant: Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.

Abstract translation: 当基于阈值电压调节半导体合金形成复杂的高k金属栅电极结构时，可以应用高效的原位工艺技术，以便在专用有源区域中形成凹槽并用半导体合金再填充凹槽。 为了在活性区域的凹陷期间减少或避免蚀刻相关的不规则性，可以控制在先前处理期间，特别是在形成沟槽隔离区域期间的铝污染程度。

公开(公告)号：US20120235245A1

公开(公告)日：2012-09-20

申请号：US13422148

申请日：2012-03-16

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/336

CPC classification number: H01L21/823481 ,  H01L21/76232 ,  H01L21/823878

Abstract: When forming sophisticated semiconductor devices on the basis of high-k metal gate electrode structures, which are to be provided in an early manufacturing stage, the encapsulation of the sensitive gate materials may be improved by reducing the depth of or eliminating recessed areas that are obtained after forming sophisticated trench isolation regions. To this end, after completing the STI module, an additional fill material may be provided so as to obtain the desired surface topography and also preserve superior material characteristics of the trench isolation regions.

Abstract translation: 当在早期制造阶段提供的高k金属栅极电极结构的基础上形成复杂的半导体器件时，可以通过减少获得的凹陷区域的深度或消除凹陷区域来改善敏感栅极材料的封装 形成复杂的沟槽隔离区。 为此，在完成STI模块之后，可以提供另外的填充材料以获得所需的表面形貌并且还保持沟槽隔离区域的优良的材料特性。

公开(公告)号：US08664066B2

公开(公告)日：2014-03-04

申请号：US13552722

申请日：2012-07-19

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  Y02P80/30

Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

Abstract translation: 本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。 为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。 以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。