- 专利标题： Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die
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申请号： US13553739申请日： 2012-07-19
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公开(公告)号： US20120280403A1公开(公告)日： 2012-11-08
- 发明人: Reza A. Pagaila , Byung Tai Do , Shuangwu Huang
- 申请人： Reza A. Pagaila , Byung Tai Do , Shuangwu Huang
- 申请人地址： SG Singapore
- 专利权人： STATS ChipPAC, Ltd.
- 当前专利权人： STATS ChipPAC, Ltd.
- 当前专利权人地址： SG Singapore
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L25/07
摘要：
A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.
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