发明申请
- 专利标题: Layout Methods of Integrated Circuits Having Unit MOS Devices
- 专利标题(中): 具有单位MOS器件的集成电路布局方法
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申请号: US13558109申请日: 2012-07-25
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公开(公告)号: US20120286368A1公开(公告)日: 2012-11-15
- 发明人: Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
- 申请人: Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 主分类号: H01L27/088
- IPC分类号: H01L27/088
摘要:
A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
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