Invention Application
- Patent Title: Connector Design for Packaging Integrated Circuits
- Patent Title (中): 封装集成电路连接器设计
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Application No.: US13343582Application Date: 2012-01-04
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Publication No.: US20120306073A1Publication Date: 2012-12-06
- Inventor: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
- Applicant: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L23/485
- IPC: H01L23/485 ; H01L21/768
Abstract:
A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
Public/Granted literature
- US08664760B2 Connector design for packaging integrated circuits Public/Granted day:2014-03-04
Information query
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