Patent search ap:"Ying-Ching Shih" Page 1

1.

发明授权
Packages and method of forming the same 有权
Title translation: 包装和形成方法

公开(公告)号：US08871568B2

公开(公告)日：2014-10-28

申请号：US13345485

申请日：2012-01-06

Applicant: Ying-Ching Shih , Szu Wei Lu , Jing-Cheng Lin

Inventor： Ying-Ching Shih , Szu Wei Lu , Jing-Cheng Lin

IPC: H01L21/58 , H01L23/485 , H01L21/78

CPC classification number: H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/3185 , H01L23/49816 , H01L24/97 , H01L2221/68345 , H01L2221/68381 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81192 , H01L2224/83005 , H01L2224/97 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00 , H01L2224/0401 , H01L2224/83

Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Abstract translation: 一种方法包括在衬底上形成电介质层，在电介质层上形成互连结构，以及将管芯结合到互连结构。然后去除衬底，并对电介质层进行图案化。连接器形成在电介质层的表面，其中连接器电耦合到管芯。

2.

发明申请
Method for Three Dimensional Integrated Circuit Fabrication 审中-公开
Title translation: 三维集成电路制作方法

公开(公告)号：US20130075892A1

公开(公告)日：2013-03-28

申请号：US13246553

申请日：2011-09-27

Applicant: Jing-Cheng Lin , Weng-Jin Wu , Ying-Ching Shih , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu

Inventor： Jing-Cheng Lin , Weng-Jin Wu , Ying-Ching Shih , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu

IPC: H01L23/48 , H01L21/50

CPC classification number: H01L23/48 , H01L21/6835 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L2221/68327 , H01L2224/0401 , H01L2224/05009 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2924/3511 , H01L2924/00012 , H01L2224/81 , H01L2924/00 , H01L2224/83

Abstract: A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 一种用于制造三维集成电路的方法包括：提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠，在第一半导体管芯的第一侧上形成模塑料层，其中多个半导体管芯被嵌入在模塑料层中。该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出，将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

3.

发明申请
Connector Design for Packaging Integrated Circuits 有权
Title translation: 封装集成电路连接器设计

公开(公告)号：US20120306073A1

公开(公告)日：2012-12-06

申请号：US13343582

申请日：2012-01-04

Applicant: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin

Inventor： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin

IPC: H01L23/485 , H01L21/768

CPC classification number: H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00

Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

Abstract translation: 一种器件包括具有顶表面的顶部电介质层。金属柱在顶部介电层的顶表面上具有一部分。在金属柱的侧壁上形成非润湿层，其中非润湿层不能熔化到熔融焊料上。焊接区域设置在金属柱上并电耦合到金属柱。

4.

发明申请
Substrate Interconnections having Different Sizes 有权
Title translation: 具有不同尺寸的基板互连

公开(公告)号：US20110285023A1

公开(公告)日：2011-11-24

申请号：US12784266

申请日：2010-05-20

Applicant: Wen-Wei Shen , Ying-Ching Shih , Chen-Shien Chen , Ming-Fa Chen

Inventor： Wen-Wei Shen , Ying-Ching Shih , Chen-Shien Chen , Ming-Fa Chen

IPC: H01L23/528 , H01L21/50

CPC classification number: H01L25/0657 , H01L21/486 , H01L23/3114 , H01L23/3192 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/81 , H01L25/0655 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/0381 , H01L2224/03831 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/1162 , H01L2224/11622 , H01L2224/1181 , H01L2224/11849 , H01L2224/11903 , H01L2224/13016 , H01L2224/13025 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13169 , H01L2224/1354 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81193 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06568 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2224/05552 , H01L2924/00

Abstract: A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

Abstract translation: 提供了可用于将一个衬底互连到另一衬底的凸块结构。导电柱形成在第一基板上，使得导电柱的宽度不同于第二基板上的接触表面。在一个实施例中，第一基板的导电柱具有梯形形状或具有锥形侧壁的形状，从而提供具有比尖端部宽的基部的导电柱。基板可以各自为集成电路管芯，插入件，印刷电路板，高密度互连等。

5.

发明授权
Stacked chip structure and fabrication method thereof 有权
Title translation: 叠片结构及其制造方法

公开(公告)号：US07541217B1

公开(公告)日：2009-06-02

申请号：US12198072

申请日：2008-08-25

Applicant: Ying-Ching Shih , Shu-Ming Chang

Inventor： Ying-Ching Shih , Shu-Ming Chang

IPC: H01L21/44

CPC classification number: H01L25/0657 , H01L24/12 , H01L24/16 , H01L24/31 , H01L24/90 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05023 , H01L2224/05568 , H01L2224/1131 , H01L2224/1147 , H01L2224/1148 , H01L2224/16 , H01L2224/2518 , H01L2224/83194 , H01L2224/90 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2224/05599 , H01L2224/05099

Abstract: A fabrication method of a stacked chip structure is provided. Firstly, a first conductive layer is formed on a first surface of a wafer. Afterwards, a first patterned polymer layer is formed on the first conductive layer, and a second patterned polymer layer is formed on a second surface of the wafer. Next, a second conductive layer is electroplated on the first conductive layer and is heated to form a number of solder bumps. After that, the wafers are stacked on a substrate structure. The first patterned polymer layer disposed on a first wafer of the wafers is correspondingly connected to the second patterned polymer layer on a second wafer of the wafers. The present invention is suitable for the stacked chip structure connected by the fine-pitch solder bumps. Besides, the fabrication of the present invention is relatively simplified.

Abstract translation: 提供了堆叠式芯片结构的制造方法。首先，在晶片的第一表面上形成第一导电层。之后，在第一导电层上形成第一图案化聚合物层，并且在晶片的第二表面上形成第二图案化聚合物层。接下来，将第二导电层电镀在第一导电层上并被加热以形成多个焊料凸点。之后，将晶片堆叠在基板结构上。设置在晶片的第一晶片上的第一图案化聚合物层相应地连接到晶片的第二晶片上的第二图案化聚合物层。本发明适用于通过细间距焊料凸块连接的堆叠芯片结构。此外，本发明的制造相对简化。

6.

发明授权
Optical subassembly of optical transceiver 有权
Title translation: 光收发器光组件

公开(公告)号：US07203426B2

公开(公告)日：2007-04-10

申请号：US11144720

申请日：2005-06-04

Applicant: Enboa Wu , Ying-Ching Shih

Inventor： Enboa Wu , Ying-Ching Shih

IPC: H04B10/00

CPC classification number: G02B6/4214 , G02B6/29361 , G02B6/4246

Abstract: A transceiver module comprised of a multiplexing/demultiplexing optical subassembly is provided. The optical subassembly includes either a transmitter module or a receiver module or both. The transmitter module has laser diodes emitting optical signals, which are reflected by reflectors, and coupled together by thin film filter. The receiver module includes thin film filters that decouple a received optical signal into constituent components. These components are reflected by reflectors to photo detectors by which the optical signals are converted into electrical signals. The reflector are capable of dual axis adjustment for adjustment of inclination thereof to effect active alignment. Further, the transmitter module and the receiver module define positioning recesses to position the laser diodes and photo detectors. The recesses are sized in accordance with the wavelengths associated with the laser diodes and photo detectors to effect passive alignment.

Abstract translation: 提供了由复用/解复用光学子组件组成的收发器模块。光学子组件包括发射器模块或接收器模块或两者。发射器模块具有发射光信号的激光二极管，其被反射器反射并通过薄膜滤波器耦合在一起。接收器模块包括将接收的光信号分离成组成部件的薄膜滤波器。这些部件被反射器反射到光电检测器，光信号将被转换成电信号。反射器能够进行双轴调节，以调整其倾斜度以实现主动对准。此外，发射器模块和接收器模块限定定位凹槽以定位激光二极管和光电检测器。根据与激光二极管和光电检测器相关联的波长来调整凹槽的大小，以实现被动对准。

7.

发明申请
Optical subassembly of optical transceiver 有权
Title translation: 光收发器光组件

公开(公告)号：US20060274999A1

公开(公告)日：2006-12-07

申请号：US11144720

申请日：2005-06-04

Applicant: Enboa Wu , Ying-Ching Shih

Inventor： Enboa Wu , Ying-Ching Shih

IPC: G02B6/42

CPC classification number: G02B6/4214 , G02B6/29361 , G02B6/4246

Abstract: A transceiver module comprised of a multiplexing/demultiplexing optical subassembly is provided. The optical subassembly includes either a transmitter module or a receiver module or both. The transmitter module has laser diodes emitting optical signals, which are reflected by reflectors, and coupled together by thin film filter. The receiver module includes thin film filters that decouple a received optical signal into constituent components. These components are reflected by reflectors to photo detectors by which the optical signals are converted into electrical signals. The reflector are capable of dual axis adjustment for adjustment of inclination thereof to effect active alignment. Further, the transmitter module and the receiver module define positioning recesses to position the laser diodes and photo detectors. The recesses are sized in accordance with the wavelengths associated with the laser diodes and photo detectors to effect passive alignment.

Abstract translation: 提供了由复用/解复用光学子组件组成的收发器模块。光学子组件包括发射器模块或接收器模块或两者。发射器模块具有发射光信号的激光二极管，其被反射器反射并通过薄膜滤波器耦合在一起。接收器模块包括将接收的光信号分离成组成部件的薄膜滤波器。这些部件被反射器反射到光电检测器，光信号将被转换成电信号。反射器能够进行双轴调节，以调整其倾斜度以实现主动对准。此外，发射器模块和接收器模块限定定位凹槽以定位激光二极管和光电检测器。根据与激光二极管和光电检测器相关联的波长来调整凹槽的大小，以实现被动对准。

8.

发明授权
Flux residue cleaning system and method 有权
Title translation: 助焊剂残渣清洗系统及方法

公开(公告)号：US09406500B2

公开(公告)日：2016-08-02

申请号：US13369138

申请日：2012-02-08

Applicant: I-Ting Chen , Ying-Ching Shih , Szu Wei Lu , Jing-Cheng Lin

Inventor： I-Ting Chen , Ying-Ching Shih , Szu Wei Lu , Jing-Cheng Lin

IPC: H01L21/02 , H01L21/67 , H01L21/48 , H01L23/00

CPC classification number: H01L21/02041 , H01L21/4864 , H01L21/67028 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/81911 , H01L2924/00014 , H01L2924/07802 , H01L2924/00 , H01L2224/0401

Abstract: A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber softens an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical. The first spray chamber removes the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue. The second immersion chamber softens the inner region of the flux residue when the wafer is immersed in a second chemical. The second spray chamber removes the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer to a predetermined standard. The drying chamber dries the wafer.

Abstract translation: 助焊剂残渣清洁系统包括第一和第二浸没室，第一和第二喷雾室以及干燥室。当晶片浸入第一化学品中时，第一浸入室软化在介于晶片和管芯之间的微胶片周围形成的焊剂残余物的外部区域。当晶片通过第一化学喷雾撞击以暴露焊剂残留物的内部区域时，第一喷雾室除去焊剂残余物的外部区域。当晶片浸入第二种化学品中时，第二浸入室软化助焊剂残余物的内部区域。当晶片被第二化学喷雾冲击时，第二喷雾室去除焊剂残余物的内部区域，以便将晶片清洁至预定的标准。干燥室干燥晶片。