发明申请
- 专利标题： Interconnect Structure for Wafer Level Package
- 专利标题（中）： 晶圆级封装的互连结构
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申请号： US13170973申请日： 2011-06-28
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公开(公告)号： US20130001776A1公开(公告)日： 2013-01-03
- 发明人: Chen-Hua Yu , Jing-Cheng Lin , Nai-Wei Liu , Jui-Pin Hung , Shin-Puu Jeng
- 申请人： Chen-Hua Yu , Jing-Cheng Lin , Nai-Wei Liu , Jui-Pin Hung , Shin-Puu Jeng
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 主分类号： H01L23/485
- IPC分类号： H01L23/485 ; H01L21/28
摘要：
A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
公开/授权文献
- US08829676B2 Interconnect structure for wafer level package 公开/授权日：2014-09-09
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