Invention Application
US20130003335A1 CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE
审中-公开
具有最小化焊盘电容的无线多层电路基板
- Patent Title: CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE
- Patent Title (中): 具有最小化焊盘电容的无线多层电路基板
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Application No.: US13612459Application Date: 2012-09-12
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Publication No.: US20130003335A1Publication Date: 2013-01-03
- Inventor: Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
- Applicant: Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Main IPC: H05K7/06
- IPC: H05K7/06
Abstract:
A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
Public/Granted literature
- US09060428B2 Coreless multi-layer circuit substrate with minimized pad capacitance Public/Granted day:2015-06-16
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