公开(公告)号：US20100017158A1

公开(公告)日：2010-01-21

申请号：US12176811

申请日：2008-07-21

Applicant: Rohan Mandrekar ,  Paul Marlan Harvey ,  Yaping Zhou ,  Kazushige Kawasaki

Inventor： Rohan Mandrekar ,  Paul Marlan Harvey ,  Yaping Zhou ,  Kazushige Kawasaki

IPC: G01R29/26

CPC classification number: G01R31/318385 ,  G01R31/318307

Abstract: A methodology to determine a bit pattern that may excite a worse case or near worse case simultaneous switching noise on a memory or input/output (IO) interface of a digital system is provided. This methodology involves determining an impedance profile of the IO interface of the digital system. The amplitude response of signal X(f) may be matched in the impedance profile of the IO interface. The phase response of the signal X(f) is also set. The signal X(f) having a matched amplitude response may be converted from a frequency domain signal to a time domain signal to produce a signal X(t). Signal X(t) the time domain signal X(t) may be digitized to represent a bit stream B(t). This bit stream may be used as a switching pattern to determine simultaneous switching noise of the IO interface of the digital system

Abstract translation: 提供了一种确定可能激发更糟糕情况或接近较差情况的位模式的方法，用于在数字系统的存储器或输入/输出（IO）接口上同时切换噪声。 该方法涉及确定数字系统的IO接口的阻抗曲线。 信号X（f）的振幅响应可以在IO接口的阻抗曲线上匹配。 信号X（f）的相位响应也被设定。 具有匹配振幅响应的信号X（f）可以从频域信号转换为时域信号以产生信号X（t）。 时域信号X（t）的信号X（t）可以被数字化以表示比特流B（t）。 该比特流可以用作切换模式以确定数字系统的IO接口的同时切换噪声

公开(公告)号：US08389870B2

公开(公告)日：2013-03-05

申请号：US12720386

申请日：2010-03-09

Applicant: Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

Inventor： Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

IPC: H05K1/11

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09718 ,  H05K2201/10734 ,  Y10T29/49124 ,  Y10T29/49151 ,  H01L2924/00

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

公开(公告)号：US09060428B2

公开(公告)日：2015-06-16

申请号：US13612459

申请日：2012-09-12

Applicant: Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Tong Kim ,  Rohan Mandrekar

Inventor： Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Tong Kim ,  Rohan Mandrekar

IPC: H05K1/16 ,  H05K1/02 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09718 ,  H05K2201/10734 ,  Y10T29/49124 ,  Y10T29/49151 ,  H01L2924/00

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract translation: 多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。 在金属层之间放置两种不同类型的绝缘层。 这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

公开(公告)号：US20130008696A1

公开(公告)日：2013-01-10

申请号：US13614314

申请日：2012-09-13

Applicant: Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

Inventor： Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

IPC: H05K1/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09718 ,  H05K2201/10734 ,  Y10T29/49124 ,  Y10T29/49151 ,  H01L2924/00

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract translation: 多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。 在金属层之间放置两种不同类型的绝缘层。 这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

公开(公告)号：US20130003335A1

公开(公告)日：2013-01-03

申请号：US13612459

申请日：2012-09-12

Applicant: Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

Inventor： Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

IPC: H05K7/06

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09718 ,  H05K2201/10734 ,  Y10T29/49124 ,  Y10T29/49151 ,  H01L2924/00

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract translation: 多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。 在金属层之间放置两种不同类型的绝缘层。 这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

公开(公告)号：US08975525B2

公开(公告)日：2015-03-10

申请号：US13614314

申请日：2012-09-13

Applicant: Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

Inventor： Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

IPC: H05K1/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09718 ,  H05K2201/10734 ,  Y10T29/49124 ,  Y10T29/49151 ,  H01L2924/00

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract translation: 多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。 在金属层之间放置两种不同类型的绝缘层。 这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

公开(公告)号：US20110222224A1

公开(公告)日：2011-09-15

申请号：US12720386

申请日：2010-03-09

Applicant: Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

Inventor： Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

IPC: G06F1/16 ,  H05K1/11 ,  H05K1/00 ,  H05K7/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09718 ,  H05K2201/10734 ,  Y10T29/49124 ,  Y10T29/49151 ,  H01L2924/00

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract translation: 多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。 在金属层之间放置两种不同类型的绝缘层。 这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。