发明申请
- 专利标题: FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD
- 专利标题(中): FUSEBAY控制器结构,系统和方法
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申请号: US13204929申请日: 2011-08-08
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公开(公告)号: US20130042166A1公开(公告)日: 2013-02-14
- 发明人: Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
- 申请人: Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: H03M13/15
- IPC分类号: H03M13/15 ; G06F11/10
摘要:
Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
公开/授权文献
- US08484543B2 Fusebay controller structure, system, and method 公开/授权日:2013-07-09
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