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公开(公告)号：US20130042166A1
公开(公告)日：2013-02-14
申请号：US13204929
申请日：2011-08-08
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译： 选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。 可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。 每个状态机可以包括当遇到其类型的校正时可以被激活的指示器，例如粘性位。 指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。
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公开(公告)号：US08484543B2
公开(公告)日：2013-07-09
申请号：US13204929
申请日：2011-08-08
IPC分类号： H03M13/00
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译： 选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。 可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。 每个状态机可以包括诸如“粘性位”的指示符，当其遇到类型的校正时可以被激活。 指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。
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3.发明授权Structure and method for storing multiple repair pass data into a fusebay 有权用于将多个修复传递数据存储到保险丝盒中的结构和方法公开(公告)号：US08467260B2
公开(公告)日：2013-06-18
申请号：US13198894
申请日：2011-08-05
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译： 相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。 每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。 连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。 在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。
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4.发明授权Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture 失效在单个保险丝架构中交织内存修复数据压缩和保险丝编程操作公开(公告)号：US08719648B2
公开(公告)日：2014-05-06
申请号：US13192051
申请日：2011-07-27
IPC分类号： G11C29/00
CPC分类号： G11C29/785 , G11C2029/0409 , H03M7/30
摘要： An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.
摘要翻译： 描述了在单个熔丝架结构中交织存储器修复数据压缩和熔丝编程操作的方法。 在一个实施例中，单个熔丝架结构包括与处理存储器修复数据压缩和熔丝编程操作的分割和交织方法一起使用的多页。 特别地，对于单个熔丝架结构中的每个页面，对存储器修复数据执行存储器修复数据压缩操作，随后对压缩存储器修复数据执行熔丝编程操作。
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5.发明申请INTERLEAVING OF MEMORY REPAIR DATA COMPRESSION AND FUSE PROGRAMMING OPERATIONS IN SINGLE FUSEBAY ARCHITECTURE 失效记忆体修复数据压缩和单个保险丝架构中的保险丝编程操作公开(公告)号：US20130031319A1
公开(公告)日：2013-01-31
申请号：US13192051
申请日：2011-07-27
IPC分类号： G06F12/06
CPC分类号： G11C29/785 , G11C2029/0409 , H03M7/30
摘要： An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.
摘要翻译： 描述了在单个熔丝架结构中交织存储器修复数据压缩和熔丝编程操作的方法。 在一个实施例中，单个熔丝架结构包括与处理存储器修复数据压缩和熔丝编程操作的分割和交织方法一起使用的多页。 特别地，对于单个熔丝架结构中的每个页面，对存储器修复数据执行存储器修复数据压缩操作，随后对压缩存储器修复数据执行熔丝编程操作。
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6.发明申请公开(公告)号：US20130033951A1
公开(公告)日：2013-02-07
申请号：US13198894
申请日：2011-08-05
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译： 相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。 每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。 连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。 在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。
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公开(公告)号：US20110029827A1
公开(公告)日：2011-02-03
申请号：US12511739
申请日：2009-07-29
CPC分类号： G11C29/14
摘要： In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.
摘要翻译： 在一个实施例中，本发明是用于集成电路芯片中的嵌入式存储器的内置自检的方法，装置和设计结构。 用于嵌入式存储器的内置自检的方法的一个实施例包括以测试时钟的速度设置多个测试图案，其中测试时钟的速度足够慢以使测试者直接与一个 芯片，其中嵌入存储器，并且其中的设置包括将用于将测试图案传送到内置自检系统的一个或多个组件的多个信号状态，将测试图案作为 高速微冲速，以速度从嵌入式存储器捕获输出数据，输出数据仅对应于测试模式之一，并且以测试时钟的速度将输出数据与期望数据进行比较。
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8.发明申请AUTOMATICALLY EXTENSIBLE ADDRESSING FOR SHARED ARRAY BUILT-IN SELF-TEST (ABIST) CIRCUITRY 有权自动进行自动测试（ABIST）电路的自动寻址公开(公告)号：US20090249146A1
公开(公告)日：2009-10-01
申请号：US12055595
申请日：2008-03-26
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3187 , G01R31/31722
摘要： A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.
摘要翻译： 一种用于通过自动扩展用于共享阵列内置自检（BIST）电路的寻址来测试集成电路（IC）的方法，包括轮询多个存储器以确定多个存储器中的哪个存储器共享第一比较树并映射 使用第一比较树将共享阵列BIST地址空间分配给多个存储器中的每一个。 另外，该方法包括估计与被测试的最大总存储器地址大小的最高有效位相对应的共享阵列BIST完成时间，重新配置共享阵列BIST电路以适应估计的共享阵列BIST完成时间并测试多个存储器共享 第一个比较树。
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9.发明授权Automatically extensible addressing for shared array built-in self-test (ABIST) circuitry 有权用于共享阵列内置自检（ABIST）电路的自动扩展寻址公开(公告)号：US07757141B2
公开(公告)日：2010-07-13
申请号：US12055595
申请日：2008-03-26
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31722
摘要： A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.
摘要翻译： 一种用于通过自动扩展用于共享阵列内置自检（BIST）电路的寻址来测试集成电路（IC）的方法，包括轮询多个存储器以确定多个存储器中的哪个存储器共享第一比较树并映射 使用第一比较树将共享阵列BIST地址空间分配给多个存储器中的每一个。 另外，该方法包括估计对应于被测试的最大总存储器地址大小的最高有效位的共享阵列BIST完成时间，重新配置共享阵列BIST电路以适应估计的共享阵列BIST完成时间并测试多个存储器共享 第一个比较树。
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10.发明申请公开(公告)号：US20090158092A1
公开(公告)日：2009-06-18
申请号：US11958680
申请日：2007-12-18
CPC分类号： G01R19/16552 , G11C11/401 , G11C29/02 , G11C29/021 , G11C29/44 , G11C2029/0401 , G11C2029/4402
摘要： The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis.
摘要翻译： 多片式电源系统的状态被指示用于修改芯片测试流程和诊断芯片故障。 接收数字符合性信号，每个合规信号与多个片上电源之一相关联。 每个电源具有相关的合规级别，并且每个合规信号指示其相关联的电源是否以相关联的合规级别运行。 合规信号被转换成指示与电源相关联的符合性信号的状态的电源状态信号。 输出电源状态信号。 如果电源工作在相关的合规级别，则输出电源状态信号表示电源正在通过。 如果电源不在其相关的合规级别运行，则输出电源状态信号表示电源出现故障。 如果电源出现故障，可能会中断内存测试，从而简化了芯片故障诊断。
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