Invention Application
US20130049124A1 MOSFET INTEGRATED CIRCUIT WITH IMPROVED SILICIDE THICKNESS UNIFORMITY AND METHODS FOR ITS MANUFACTURE
审中-公开
具有改进的硅酸盐厚度均匀的MOSFET集成电路及其制造方法
- Patent Title: MOSFET INTEGRATED CIRCUIT WITH IMPROVED SILICIDE THICKNESS UNIFORMITY AND METHODS FOR ITS MANUFACTURE
- Patent Title (中): 具有改进的硅酸盐厚度均匀的MOSFET集成电路及其制造方法
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Application No.: US13223016Application Date: 2011-08-31
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Publication No.: US20130049124A1Publication Date: 2013-02-28
- Inventor: Clemens Fitz , Stephan Waidmann , Stefan Flachowsky , Peter Baars , Rainer Giedigkeit
- Applicant: Clemens Fitz , Stephan Waidmann , Stefan Flachowsky , Peter Baars , Rainer Giedigkeit
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/3205

Abstract:
An MOSFET device having a Silicide layer of uniform thickness and which is substantially free of “Spotty” NiSi-type holes, and methods for its fabrication, are provided. One such method involves simultaneously depositing a metal layer (e.g. Ni) over the active and open areas of a semiconductor substrate. The depth to which some or all of the metal is transferred into the substrate is determined by thermal budget. A rapid thermal annealing process is employed to produce a NiSi layer of a uniform thickness in both the active and open areas. Upon achieving a NiSi layer of a desired thickness, the excess metal is removed from the substrate surface.
Public/Granted literature
- US1233087A Parachute. Public/Granted day:1917-07-10
Information query
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