Invention Application
US20130069134A1 MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES
失效
包含两个浮动门结构的晶体管的存储器
- Patent Title: MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES
- Patent Title (中): 包含两个浮动门结构的晶体管的存储器
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Application No.: US13608436Application Date: 2012-09-10
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Publication No.: US20130069134A1Publication Date: 2013-03-21
- Inventor: Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
- Applicant: Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
- Priority: JP2011-201867 20110915
- Main IPC: H01L27/11
- IPC: H01L27/11
Abstract:
In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.
Public/Granted literature
- US08610196B2 Memory including transistors with double floating gate structures Public/Granted day:2013-12-17
Information query
IPC分类:
