公开(公告)号：US08610196B2

公开(公告)日：2013-12-17

申请号：US13608436

申请日：2012-09-10

申请人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

发明人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

IPC分类号： H01L27/11

CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

公开(公告)号：US20130069134A1

公开(公告)日：2013-03-21

申请号：US13608436

申请日：2012-09-10

申请人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

发明人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

IPC分类号： H01L27/11

CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

公开(公告)号：US08779502B2

公开(公告)日：2014-07-15

申请号：US13316603

申请日：2011-12-12

申请人： Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

发明人： Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L21/70 ,  H01L21/336

CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案 第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧 第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态 第i个半导体层的第2方向。

公开(公告)号：US20120139030A1

公开(公告)日：2012-06-07

申请号：US13316603

申请日：2011-12-12

申请人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

发明人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案 第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧 第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态 第i个半导体层的第2方向。

公开(公告)号：US20110049611A1

公开(公告)日：2011-03-03

申请号：US12769951

申请日：2010-04-29

申请人： Masahiro Kiyotoshi ,  Atsuhiro Kinoshita ,  Kiwamu Sakuma ,  Koichi Muraoka ,  Ichiro Mizushima

发明人： Masahiro Kiyotoshi ,  Atsuhiro Kinoshita ,  Kiwamu Sakuma ,  Koichi Muraoka ,  Ichiro Mizushima

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881

摘要： In a memory cell portion, a stacked structure, in which dielectric layers and semiconductor layers are alternately stacked, is arranged in a fin shape on a semiconductor substrate, and in a peripheral circuit portion, a gate electrode is arranged on the semiconductor substrate via a gate dielectric film so that a height of an upper surface of the gate electrode is set to be substantially equal to a height of an upper surface of the stacked structure in which the dielectric layers and the semiconductor layers are alternately stacked.

摘要翻译： 在存储单元部分中，电介质层和半导体层交替层叠的堆叠结构在半导体衬底上以翅片形状布置，并且在外围电路部分中，栅电极经由 使得栅极电极的上表面的高度被设定为与电介质层和半导体层交替层叠的层叠结构的上表面的高度大致相等。

公开(公告)号：US09379320B2

公开(公告)日：2016-06-28

申请号：US13362832

申请日：2012-01-31

申请人： Masao Shingu ,  Akira Takashima ,  Koichi Muraoka

发明人： Masao Shingu ,  Akira Takashima ,  Koichi Muraoka

IPC分类号： H01L45/00 ,  H01L27/06 ,  H01L27/24 ,  H01L27/10

CPC分类号： H01L45/1273 ,  H01L27/101 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.

摘要翻译： 根据一个实施例，非易失性存储器件包括存储器部分。 存储部分包括第一绝缘层，第二绝缘层和一对电极。 第二绝缘层形成在第一绝缘层上并与第一绝缘层接触。 第二绝缘层具有与第一绝缘层的组成不同的组成和与第一绝缘层的相位状态不同的相位状态中的至少一个。 一对电极能够使电流通过沿着第一绝缘层和第二绝缘层之间的边界部分的电流路径。 通过施加在该对电极之间的电压来改变电流路径的电阻。

公开(公告)号：US08319271B2

公开(公告)日：2012-11-27

申请号：US13182283

申请日：2011-07-13

申请人： Shoko Kikuchi ,  Yasushi Nakasaki ,  Koichi Muraoka

发明人： Shoko Kikuchi ,  Yasushi Nakasaki ,  Koichi Muraoka

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

摘要： The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide, a first control gate electrode, and a first source/drain region. The select transistor includes a third insulating film on the semiconductor substrate, a fourth insulating film made of an aluminum oxide containing at least one of a tetravalent cationic element, a pentavalent cationic element, and N (nitrogen), a second control gate electrode, and a second source/drain region.

摘要翻译： 本发明提供一种在选择晶体管中使用氧化铝膜作为栅绝缘膜的一部分的高性能MONOS型NAND型非易失性半导体存储器件，并且作为存储晶体管中的块绝缘膜。 NAND型非易失性半导体存储器件在半导体衬底上具有串联连接的多个存储单元晶体管和选择晶体管。 存储单元晶体管包括半导体衬底上的第一绝缘膜，电荷俘获层，由氧化铝制成的第二绝缘膜，第一控制栅极电极和第一源极/漏极区域。 选择晶体管包括半导体衬底上的第三绝缘膜，由包含四价阳离子元素，五价阳离子元素和N（氮）中的至少一种的氧化铝制成的第四绝缘膜，第二控制栅电极和 第二源极/漏极区域。

公开(公告)号：US08278644B2

公开(公告)日：2012-10-02

申请号：US12710942

申请日：2010-02-23

申请人： Shosuke Fujii ,  Koichi Muraoka

发明人： Shosuke Fujii ,  Koichi Muraoka

IPC分类号： H01L29/06

CPC分类号： H01L29/51 ,  H01L29/1606 ,  H01L29/7781 ,  H01L29/78

摘要： A switching device includes: a first layer including a carbon material having a six-member ring network structure; a first electrode electrically connected to a first portion of the first layer; a second electrode electrically connected to a second portion of the first layer and provided apart from the first electrode; a third electrode including a fourth portion provided opposing a third portion between the first portion and the second portion of the first layer; and a second layer provided between the third portion of the first layer and the fourth portion of the third electrode. The second layer includes: a base portion; and a functional group portion. The functional group portion is provided between the base portion and the first layer. The functional group portion is bonded to the base portion. A ratio of sp2-bonded carbon and sp3-bonded carbon of the first layer is changeable by a voltage applied between the first layer and the third electrode.

摘要翻译： 开关装置包括：第一层，包括具有六元环网结构的碳材料; 电连接到第一层的第一部分的第一电极; 电连接到第一层的第二部分并且与第一电极分开设置的第二电极; 第三电极，包括与所述第一层的第一部分和第二部分之间的第三部分相对设置的第四部分; 以及设置在第一层的第三部分和第三电极的第四部分之间的第二层。 第二层包括：基部; 和官能团部分。 功能组部分设置在基部和第一层之间。 官能团部分结合到基部。 第一层的sp2键合碳和sp3键合碳的比例可以通过施加在第一层和第三电极之间的电压而改变。

公开(公告)号：US08217444B2

公开(公告)日：2012-07-10

申请号：US13194099

申请日：2011-07-29

申请人： Yasushi Nakasaki ,  Koichi Muraoka ,  Naoki Yasuda ,  Shoko Kikuchi

发明人： Yasushi Nakasaki ,  Koichi Muraoka ,  Naoki Yasuda ,  Shoko Kikuchi

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/7881

摘要： A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al2O3.

摘要翻译： 一种能够电写入，擦除，读取和保留数据的MONOS型非易失性半导体存储器件，所述存储器件包括源极/漏极区，第一栅极绝缘层，形成在第一栅极绝缘层上的第一电荷俘获层 形成在第一电荷俘获层上的第二栅极绝缘层，以及形成在第二栅极绝缘层上的控制电极。 第一电荷俘获层包括含有Al和O作为主要元素并且具有由间隙O原子和四价阳离子原子的复合物形成的缺陷对的绝缘膜，代替Al原子，绝缘膜还具有电子未占有的含量 从Al2O3的价带最大值测量的2eV-6eV的范围。

公开(公告)号：US20100080062A1

公开(公告)日：2010-04-01

申请号：US12411746

申请日：2009-03-26

申请人： Jun Fujiki ,  Koichi Muraoka ,  Naoki Yasuda

发明人： Jun Fujiki ,  Koichi Muraoka ,  Naoki Yasuda

IPC分类号： G11C16/04 ,  H01L29/792 ,  G11C5/14 ,  G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11565 ,  H01L27/11568

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate including a first channel, and a source region and a drain region provided on both sides of the first channel; a first insulating film provided on the first channel; a charge retention layer provided on the first insulating film; a second insulating film provided on the charge retention layer; and a semiconductor layer including a second channel provided on the second insulating film, and a source region and a drain region provided on both sides of the second channel.

摘要翻译： 非易失性半导体存储器件包括：包括第一沟道的半导体衬底和设置在第一沟道两侧的源极区和漏极区; 设置在第一通道上的第一绝缘膜; 设置在所述第一绝缘膜上的电荷保持层; 设置在电荷保持层上的第二绝缘膜; 以及包括设置在第二绝缘膜上的第二通道的半导体层，以及设置在第二通道两侧的源极区域和漏极区域。