发明申请
US20130113547A1 Method and apparatus for floating or applying voltage to a well of an integrated circuit
有权
用于浮动或向集成电路的阱施加电压的方法和装置
- 专利标题: Method and apparatus for floating or applying voltage to a well of an integrated circuit
- 专利标题(中): 用于浮动或向集成电路的阱施加电压的方法和装置
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申请号: US13374335申请日: 2011-12-22
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公开(公告)号: US20130113547A1公开(公告)日: 2013-05-09
- 发明人: Victor Moroz , Jamil Kawa , James D. Sproch , Robert B. Lefferts
- 申请人: Victor Moroz , Jamil Kawa , James D. Sproch , Robert B. Lefferts
- 申请人地址: US CA Mountain View
- 专利权人: Synopsys. Inc.
- 当前专利权人: Synopsys. Inc.
- 当前专利权人地址: US CA Mountain View
- 主分类号: G05F1/10
- IPC分类号: G05F1/10
摘要:
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.
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