-
公开(公告)号：US06370071B1
公开(公告)日：2002-04-09
申请号：US09660707
申请日：2000-09-13
IPC分类号： G11C700
摘要： A high voltage CMOS switch circuit having an arrangement of device connections such that the individual transistor devices are substantially the same size, improving performance while reducing size and providing breakdown protection. The circuit switches a high voltage to the output based on a low voltage input. The circuit is ratio-less and self-biased, capable of operating a very low supply voltage compared to the state of the art.
摘要翻译： 具有设备连接布置的高压CMOS开关电路，使得各个晶体管器件的尺寸基本相同，在减小尺寸并提供击穿保护的同时提高性能。 电路基于低电压输入将高电压切换到输出。 与现有技术相比，该电路是无比的和自偏压的，能够操作非常低的电源电压。
-
2.发明授权System and method for embedding a sub-channel in a block coded data stream 有权用于将子信道嵌入到块编码数据流中的系统和方法公开(公告)号：US07158575B2
公开(公告)日：2007-01-02
申请号：US10222071
申请日：2002-08-16
CPC分类号： H04L1/0057 , H04L25/03038 , H04L25/03343 , H04L25/03885 , H04L2025/03363 , H04L2025/03815
摘要： The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs a variable rate back channel, incorporated within an existing communication that does not increase or adversely impact the transmission rate of data on the communication channel.
摘要翻译： 本发明一般涉及通过通信信道提供高速数字通信的方法，装置和制品。 一方面，本发明采用并入在现有通信中的可变速率反向信道，其不会增加或不利地影响通信信道上的数据的传输速率。
-
公开(公告)号：US09287253B2
公开(公告)日：2016-03-15
申请号：US13374335
申请日：2011-12-22
申请人： Victor Moroz , Jamil Kawa , James D. Sproch , Robert B. Lefferts
发明人： Victor Moroz , Jamil Kawa , James D. Sproch , Robert B. Lefferts
IPC分类号： H01L27/02 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0928
摘要： In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.
-
公开(公告)号：US08208591B2
公开(公告)日：2012-06-26
申请号：US12819629
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H04B1/10
CPC分类号： H04L25/03019 , H04L2025/03617 , H04L2025/03656 , H04L2025/037
摘要： Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.
摘要翻译： 描述了用于适配和/或优化接收机的均衡器的系统和技术。 可以通过修改一个或多个均衡参数来调整均衡器的行为。 在适应和/或优化过程的开始时，系统可以确定一个或多个均衡参数的鲁棒的初始值。 然后，系统可以通过迭代地调整一个或多个均衡参数来适应和/或优化均衡器。 具体来说，在每个迭代中，系统可以使用接收机的时钟和数据恢复（CDR）电路来确定与一个或多个数据模式相关联的早期和晚期数据转换的数量。 接下来，系统可以调整一个或多个均衡参数，使得对于一个或多个数据模式中的每个数据模式，早期数据转换的数量与后期数据转换的数量之间的比率基本上等于期望值 。
-
公开(公告)号：US20110310947A1
公开(公告)日：2011-12-22
申请号：US12819629
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H03H7/30
CPC分类号： H04L25/03019 , H04L2025/03617 , H04L2025/03656 , H04L2025/037
摘要： Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.
摘要翻译： 描述了用于适配和/或优化接收机的均衡器的系统和技术。 可以通过修改一个或多个均衡参数来调整均衡器的行为。 在适应和/或优化过程的开始时，系统可以确定一个或多个均衡参数的鲁棒的初始值。 然后，系统可以通过迭代地调整一个或多个均衡参数来适应和/或优化均衡器。 具体来说，在每个迭代中，系统可以使用接收机的时钟和数据恢复（CDR）电路来确定与一个或多个数据模式相关联的早期和晚期数据转换的数量。 接下来，系统可以调整一个或多个均衡参数，使得对于一个或多个数据模式中的每个数据模式，早期数据转换的数量与后期数据转换的数量之间的比率基本上等于期望值 。
-
6.发明授权System and method for embedding a sub-channel in a block coded data stream 有权用于将子信道嵌入到块编码数据流中的系统和方法公开(公告)号：US07345992B2
公开(公告)日：2008-03-18
申请号：US10659943
申请日：2003-09-11
CPC分类号： H04L1/0057 , H04L25/03038 , H04L25/03343 , H04L25/03885 , H04L2025/03363 , H04L2025/03815
摘要： The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs a variable rate back channel, incorporated within an existing communication that does not increase or adversely impact the transmission rate of data on the communication channel.
摘要翻译： 本发明一般涉及通过通信信道提供高速数字通信的方法，装置和制品。 一方面，本发明采用并入在现有通信中的可变速率反向信道，其不会增加或不利地影响通信信道上的数据的传输速率。
-
7.发明授权公开(公告)号：US08976497B2
公开(公告)日：2015-03-10
申请号：US13477971
申请日：2012-05-22
CPC分类号： H02H9/04 , H01L27/0251 , H02H3/02 , H02H9/046
摘要： An electrostatic discharge (ESD) device implemented within a power domain to mitigate ESD events imparted from another power domain for reducing integrated circuit (IC) failures. A first power domain includes an interface where ESD events are received and an output that can impart ESD event voltages on other components. A second power domain includes an ESD device coupled to the output of the first power domain and a protected IC. In one embodiment, the ESD device includes a floating device with an input terminal coupled to the interface output. By floating the device receiving the ESD event in the second power domain, damaging ESD induced voltages are reduced. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration.
摘要翻译： 在功率域内实现的静电放电（ESD）器件，以减轻从另一个电源域传递的ESD事件，以减少集成电路（IC）故障。 第一功率域包括接收ESD事件的接口以及可以在其他部件上传递ESD事件电压的输出。 第二功率域包括耦合到第一功率域的输出的ESD器件和受保护的IC。 在一个实施例中，ESD装置包括具有耦合到接口输出的输入端的浮动装置。 通过将接收到ESD事件的设备悬空在第二个电源域中，损害ESD感应电压就会降低。 可以使用标准单元库来实现ESD器件的实施例，以简化集成。
-
公开(公告)号：US20110311009A1
公开(公告)日：2011-12-22
申请号：US12819660
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H04L7/00
CPC分类号： H04L1/205 , G01R13/0218
摘要： An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.
摘要翻译： 描述了一个模内范围。 在线范围可以包括一个或多个范围限幅器，相位扫描电路，电压扫描电路和眼图数据收集电路。 时钟和数据恢复电路可以接收输入信号，并输出恢复的时钟信号和恢复的比特流。 相位扫描电路可以接收恢复的时钟信号，并通过向恢复的时钟信号添加相位偏移来输出示波器时钟信号。 示波器限幅器可以接收电压阈值，示波器时钟信号和输入信号，并输出示波器位流。 眼图数据收集电路可以检测恢复的比特流中的一个或多个比特模式，并且单独或部分地基于范围比特流和恢复的比特流来修改一个或多个范围计数器的值。
-
公开(公告)号：US5670907A
公开(公告)日：1997-09-23
申请号：US403595
申请日：1995-03-14
申请人： James Gorecki , Ravindar Lall , Robert B. Lefferts
发明人： James Gorecki , Ravindar Lall , Robert B. Lefferts
IPC分类号： H01L27/04 , G05F3/20 , G05F3/26 , G11C5/14 , G11C11/408 , H01L21/822 , H02M3/07 , H03K19/094 , G05F1/10
摘要： An embodiment of a pumped substrate system includes an oscillator, capacitive pump, comparing circuit, and a level shifter. The level shifter is coupled between the substrate and the positive input lead of the comparator and shifts the voltage level present on the substrate by a voltage Vbg. The comparator compares ground potential to the shifted substrate voltage. The oscillator, capacitive pump and comparing circuit form a negative feedback loop which operates to maintain the substrate voltage substantially equal to -Vbg. In one embodiment, the level shifter includes a band gap reference.
摘要翻译： 泵浦衬底系统的实施例包括振荡器，电容泵，比较电路和电平转换器。 电平移位器耦合在比较器的衬底和正输入引线之间，并且通过电压Vbg将存在于衬底上的电压电平移位。 比较器将接地电位与移位的衬底电压进行比较。 振荡器，电容泵和比较电路形成负反馈回路，其操作以将衬底电压维持在基本上等于-Vbg。 在一个实施例中，电平移位器包括带隙基准。
-
公开(公告)号：US20130314824A1
公开(公告)日：2013-11-28
申请号：US13477971
申请日：2012-05-22
IPC分类号： H02H9/04
CPC分类号： H02H9/04 , H01L27/0251 , H02H3/02 , H02H9/046
摘要： An electrostatic discharge (ESD) device implemented within a power domain to mitigate ESD events imparted from another power domain for reducing integrated circuit (IC) failures. A first power domain includes an interface where ESD events are received and an output that can impart ESD event voltages on other components. A second power domain includes an ESD device coupled to the output of the first power domain and a protected IC. In one embodiment, the ESD device includes a floating device with an input terminal coupled to the interface output. By floating the device receiving the ESD event in the second power domain, damaging ESD induced voltages are reduced. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration.
摘要翻译： 在功率域内实现的静电放电（ESD）器件，以减轻从另一个电源域传递的ESD事件，以减少集成电路（IC）故障。 第一功率域包括接收ESD事件的接口以及可以将ESD事件电压传递到其他部件上的输出。 第二功率域包括耦合到第一功率域的输出的ESD器件和受保护的IC。 在一个实施例中，ESD装置包括具有耦合到接口输出的输入端的浮动装置。 通过将接收到ESD事件的设备悬空在第二个电源域中，损害ESD感应电压就会降低。 可以使用标准单元库来实现ESD器件的实施例，以简化集成。
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.012 秒)
