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    THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP
    1.
    发明申请
    THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP 审中-公开
    通过控制的S / D底线调整晶体管的阈值

    公开(公告)号：US20130026575A1

    公开(公告)日：2013-01-31

    申请号：US13193320

    申请日：2011-07-28

    Applicant: Victor Moroz ,  James D. Sproch

    Inventor： Victor Moroz ,  James D. Sproch

    IPC: H01L27/12 ,  H01L21/336

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/78618

    Abstract: Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff.

    Abstract translation: 粗略地描述，集成电路器件已经在衬底上形成多个晶体管，其包括至少一个晶体管的第一子集和至少一个晶体管的第二子集，其中第一子集中的所有晶体管具有一个下层距离，并且全部 的第二子集中的晶体管具有不同的底层距离。 第一和第二子集中的晶体管优选地具有不同的阈值电压，并且优选地在高性能/低功率权衡上实现不同的点。

    Video dot intensity balancer
    3.
    发明授权
    Video dot intensity balancer 失效
    视频点强度平衡器

    公开(公告)号：US4719456A

    公开(公告)日：1988-01-12

    申请号：US709438

    申请日：1985-03-08

    Applicant: James D. Sproch ,  Morton B. Herman

    Inventor： James D. Sproch ,  Morton B. Herman

    IPC: G09G1/00 ,  G09G1/16

    CPC classification number: G09G1/002

    Abstract: A video dot intensity balancer for use in a video display system wherein information is represented by a series of logic bits in a video stream corresponding to dots to be displayed on a CRT is disclosed. Logic elements are coupled to the output of a bit generator for comparing adjacent bits and outputting an information-defining signal wherein a single information-defining bit never stands alone. In this manner, apparent intensity imbalances on the video screen are eliminated.

    Abstract translation: 公开了一种在视频显示系统中使用的视频点强度平衡器，其中信息由对应于要显示在CRT上的点的视频流中的一系列逻辑位表示。 逻辑元件耦合到比特发生器的输出，用于比较相邻比特并输出信息定义信号，其中单个信息定义比特永远不会独立。 以这种方式，消除了视频屏幕上的视在强度不平衡。

    Method and system for pipe stage gating within an operating pipelined circuit for power savings
    5.
    发明授权
    Method and system for pipe stage gating within an operating pipelined circuit for power savings 有权
    用于节电的操作流水线电路中的管道浇口的方法和系统

    公开(公告)号：US06247134B1

    公开(公告)日：2001-06-12

    申请号：US09283128

    申请日：1999-03-31

    Applicant: James D. Sproch ,  Michael Münch ,  Renu Mehra

    Inventor： James D. Sproch ,  Michael Münch ,  Renu Mehra

    IPC: G06F132

    CPC classification number: G06F9/3869 ,  G06F1/3287 ,  G06F9/3832 ,  G06F9/3867 ,  Y02D10/171

    Abstract: A method and system for power savings within a pipelined design by performing intelligent stage gating. The present invention recognizes that not every operand applied to the input of a pipeline requires a recomputation in the different pipeline stages. Circuitry is used to generate a signal, C, indicating that this condition holds. C is then used to gate the register bank at the input of the first pipeline stage thereby potentially saving power in the register bank. Moreover, C can also be stored in a register, the output of which: a) gates the register bank of the second stage; and b) connects to another register to store signal C to be used in the third stage. Power savings is provided by not clocking the register circuit of the stage, and in some instances, power is saved within the stage's associated combinational logic. In one embodiment, a register (to store C) is added in each stage of a pipeline to use C as a gating signal in the subsequent stage. This yields a structure in which signal C propagates through the pipeline in synchronization with the clock, successively gating the associated register banks. The value of C is generated whenever the output of the stage is inconsequential. For example, the output can be inconsequential in cases when duplicate operands are received in back-to-back clock cycles. Also, in maximum and minimum cases a operand that is not larger or smaller, respectively, than the largest or smallest previously received operand can yield an inconsequential result.

    Abstract translation: 通过执行智能阶段门控，在流水线设计中节能的方法和系统。 本发明认识到，不是应用于流水线的输入的每个操作数都不需要在不同的流水线级重新计算。 电路用于产生指示该条件成立的信号C。 C然后用于在第一流水线级的输入端对门限寄存器组进行门控，从而潜在地节省了寄存器组的功率。 此外，C也可以存储在寄存器中，其输出：a）门控第二级的寄存器组; 并且b）连接到另一寄存器以存储要在第三级中使用的信号C. 通过不对该级的寄存器电路进行计时来提供功率节省，并且在一些情况下，功率节省在该相​​关联的组合逻辑内。 在一个实施例中，在流水线的每个级中添加一个寄存器（存储C），以便在后续阶段使用C作为门控信号。 这产生了其中信号C与时钟同步地通过流水线传播的结构，连续地选通相关联的寄存器组。 只要阶段的输出无关紧要，就产生C的值。 例如，在背靠背时钟周期接收到重复操作数的情况下，输出可能无关紧要。 此外，在最大和最小情况下，分别不大于或小于最大或最小的先前接收的操作数的操作数可能产生无关紧要的结果。

    Method and apparatus for floating or applying voltage to a well of an integrated circuit
    7.
    发明申请
    Method and apparatus for floating or applying voltage to a well of an integrated circuit 有权
    用于浮动或向集成电路的阱施加电压的方法和装置

    公开(公告)号：US20130113547A1

    公开(公告)日：2013-05-09

    申请号：US13374335

    申请日：2011-12-22

    Applicant: Victor Moroz ,  Jamil Kawa ,  James D. Sproch ,  Robert B. Lefferts

    Inventor： Victor Moroz ,  Jamil Kawa ,  James D. Sproch ,  Robert B. Lefferts

    IPC: G05F1/10

    CPC classification number: H01L27/0207 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928

    Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

    Abstract translation: 在一个阱偏压布置中，没有良好的偏置电压施加到n阱，并且没有良好的偏置电压施加到p阱。 由于没有施加外部阱偏置电压，即使在n阱和p阱中的器件的操作期间，n阱和p阱都是浮置的。 在另一井偏压装置中，最低可用电压不施加到p阱，例如接地电压，或施加到p阱中n型晶体管的n +掺杂源极区的电压。 即使在p阱中的n型晶体管的操作期间也发生这种情况。 在另一个阱偏压装置中，最高可用电压不施加到n阱，例如电源电压，或施加到n阱中p型晶体管的p +掺杂源极区的电压。 即使在n阱中的p型晶体管的操作期间也会发生这种情况。

    Virtual ground read only memory
    10.
    发明授权
    Virtual ground read only memory 失效
    虚拟地面只读存储器

    公开(公告)号：US4638459A

    公开(公告)日：1987-01-20

    申请号：US696591

    申请日：1985-01-31

    Applicant: Henry W. Pechar, Jr. ,  James D. Sproch

    Inventor： Henry W. Pechar, Jr. ,  James D. Sproch

    IPC: G11C17/12 ,  G11C17/00

    CPC classification number: G11C17/12

    Abstract: A dynamic read only memory (ROM) which comprises a memory select precharge section, a memory select section, a memory section, a memory precharge section and a plurality of grounding devices. The ground reference for the pulldown transistors is selectively activated at an appropriate time such that the memory sections are active only for a relatively brief portion of the memory cycle, thereby reducing dc power consumption and simplifying the driver circuit.

    Abstract translation: 一种动态只读存储器（ROM），其包括存储器选择预充电部分，存储器选择部分，存储部分，存储器预充电部分和多个接地装置。 下拉晶体管的接地参考在适当的时间被选择性地激活，使得存储器部分仅对于存储器周期的相当短的部分是有效的，从而减少直流功率消耗并简化驱动器电路。

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