发明申请
US20130119533A1 Package for Three Dimensional Integrated Circuit 有权
三维集成电路封装

Package for Three Dimensional Integrated Circuit
摘要:
A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.
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