发明申请
- 专利标题: Package for Three Dimensional Integrated Circuit
- 专利标题(中): 三维集成电路封装
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申请号: US13297992申请日: 2011-11-16
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公开(公告)号: US20130119533A1公开(公告)日: 2013-05-16
- 发明人: Chih-Hao Chen , Long Hua Lee , Chun-Hsing Su , Yi-Lin Tsai , Kung-Chen Yeh , Chung Yu Wang , Jui-Pin Hung , Jing-Cheng Lin
- 申请人: Chih-Hao Chen , Long Hua Lee , Chun-Hsing Su , Yi-Lin Tsai , Kung-Chen Yeh , Chung Yu Wang , Jui-Pin Hung , Jing-Cheng Lin
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L21/78
摘要:
A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.
公开/授权文献
- US08772929B2 Package for three dimensional integrated circuit 公开/授权日:2014-07-08