发明申请
US20130176771A1 8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES 有权
具有外部门极二极管的8晶体管SRAM单元设计

8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES
摘要:
An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
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