A DMA controller comprises a reading start address register storing a reading start address from which reading starts; a reading data size register storing the size of data to be read in a single reading operation; an offset value register storing an offset value for updating the reading start address after the reading operation ends; a repetition upper limit value register storing the upper limit value of the number of times of repetition of the reading operation; and a repetition counter register storing the number of times of repetition of the reading operation. The controller of the DMA controller outputs an interrupt signal indicating that the processing of the DMA controller ends when the value stored in the repetition counter register reaches the value stored in the repetition upper limit value register.