Invention Application
- Patent Title: SEMICONDUCTOR MEMORY DEVICE
- Patent Title (中): 半导体存储器件
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Application No.: US13600448Application Date: 2012-08-31
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Publication No.: US20130229854A1Publication Date: 2013-09-05
- Inventor: Yoichi MINEMURA , Takayuki TSUKAMOTO , Hiroshi KANNO , Takamasa OKAWA
- Applicant: Yoichi MINEMURA , Takayuki TSUKAMOTO , Hiroshi KANNO , Takamasa OKAWA
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Priority: JP2011-265984 20111205
- Main IPC: G11C13/00
- IPC: G11C13/00

Abstract:
A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.
Public/Granted literature
- US08665634B2 Semiconductor memory device Public/Granted day:2014-03-04
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