发明申请
US20130272072A1 BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN TEST VALUES
有权
用于存储器件的旁路结构和减少未知测试值的方法
- 专利标题: BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN TEST VALUES
- 专利标题(中): 用于存储器件的旁路结构和减少未知测试值的方法
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申请号: US13444229申请日: 2012-04-11
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公开(公告)号: US20130272072A1公开(公告)日: 2013-10-17
- 发明人: Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
- 申请人: Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: G11C7/10
- IPC分类号: G11C7/10
摘要:
Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.