公开(公告)号：US08917566B2

公开(公告)日：2014-12-23

申请号：US13444229

申请日：2012-04-11

申请人： Aaron J. Cummings ,  Michael T. Fragano ,  Kevin W. Gorman ,  Kelly A. Ockunzzi ,  Michael R. Ouellette

发明人： Aaron J. Cummings ,  Michael T. Fragano ,  Kevin W. Gorman ,  Kelly A. Ockunzzi ,  Michael R. Ouellette

IPC分类号： G11C7/00

CPC分类号： G11C29/56004

摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.

摘要翻译： 本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。 在一个实施例中，公开了一种用于存储器件的旁路结构。 旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于 断言测试信号，使得来自存储器设备的输出的未知数据被旁路。

公开(公告)号：US20130272072A1

公开(公告)日：2013-10-17

申请号：US13444229

申请日：2012-04-11

申请人： Aaron J. Cummings ,  Michael T. Fragano ,  Kevin W. Gorman ,  Kelly A. Ockunzzi ,  Michael R. Ouellette

发明人： Aaron J. Cummings ,  Michael T. Fragano ,  Kevin W. Gorman ,  Kelly A. Ockunzzi ,  Michael R. Ouellette

IPC分类号： G11C7/10

CPC分类号： G11C29/56004

摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.

摘要翻译： 本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。 在一个实施例中，公开了一种用于存储器件的旁路结构。 旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于 断言测试信号，使得来自存储器设备的输出的未知数据被旁路。