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公开(公告)号：US06882159B1
公开(公告)日：2005-04-19
申请号：US10707172
申请日：2003-11-25
IPC分类号： G01R31/01 , G01R31/317
CPC分类号： G01R31/31704 , G01R31/31723
摘要： A structure and associated method for associated grouping of an alpha device with a plurality of dependent devices for a manufacturing test. The alpha device comprises at least one electrical characteristic. The plurality of dependent devices each comprise the at least one electrical characteristic. The alpha device and the plurality dependent devices are grouped together within a semiconductor device for an associated manufacturing test.
摘要翻译： 一种用于制造测试的用于将α设备与多个依赖设备相关联的组合的结构和相关联的方法。 该α装置包括至少一个电特性。 多个依赖装置各自包括至少一个电特性。 α设备和多个依赖设备在用于相关联的制造测试的半导体器件内分组在一起。
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2.发明授权Bypass structure for a memory device and method to reduce unknown test values 有权用于存储器件的旁路结构和减少未知测试值的方法公开(公告)号：US08917566B2
公开(公告)日：2014-12-23
申请号：US13444229
申请日：2012-04-11
申请人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
发明人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
IPC分类号： G11C7/00
CPC分类号： G11C29/56004
摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.
摘要翻译： 本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。 在一个实施例中，公开了一种用于存储器件的旁路结构。 旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于 断言测试信号，使得来自存储器设备的输出的未知数据被旁路。
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3.发明申请BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN TEST VALUES 有权用于存储器件的旁路结构和减少未知测试值的方法公开(公告)号：US20130272072A1
公开(公告)日：2013-10-17
申请号：US13444229
申请日：2012-04-11
申请人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
发明人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
IPC分类号： G11C7/10
CPC分类号： G11C29/56004
摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.
摘要翻译： 本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。 在一个实施例中，公开了一种用于存储器件的旁路结构。 旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于 断言测试信号，使得来自存储器设备的输出的未知数据被旁路。
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4.发明授权Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit) 失效提供嵌入在ASIC（专用集成电路）中的第三方宏电路的测试访问机制公开(公告)号：US07734968B2
公开(公告)日：2010-06-08
申请号：US11831318
申请日：2007-07-31
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318519
摘要： Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuits). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.
摘要翻译： 嵌入在ASIC（专用集成电路）中的FPGA（现场可编程门阵列）的新型结构和测试方法。 基本上，在FPGA和ASIC之间耦合了移位/接口系统。 在正常操作期间，移位/接口系统将FPGA电耦合到ASIC。 在测试FPGA期间，移位/接口系统将FPGA测试数据串行扫描，然后将FPGA测试数据提供给FPGA，然后从FPGA接收FPGA响应数据，然后逐个扫描FPGA响应数据。 在ASIC测试期间，移位/接口系统以ASIC测试数据串行扫描，然后将ASIC测试数据馈送到ASIC，然后从ASIC接收ASIC响应数据，然后串行扫描ASIC响应数据。
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5.发明授权Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit) 失效提供嵌入在ASIC（专用集成电路）中的第三方宏电路的测试访问机制公开(公告)号：US07308630B2
公开(公告)日：2007-12-11
申请号：US10906467
申请日：2005-02-22
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318519
摘要： Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuit). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.
摘要翻译： 嵌入在ASIC（专用集成电路）中的FPGA（现场可编程门阵列）的新型结构和测试方法。 基本上，在FPGA和ASIC之间耦合了移位/接口系统。 在正常操作期间，移位/接口系统将FPGA电耦合到ASIC。 在测试FPGA期间，移位/接口系统将FPGA测试数据串行扫描，然后将FPGA测试数据提供给FPGA，然后从FPGA接收FPGA响应数据，然后逐个扫描FPGA响应数据。 在ASIC测试期间，移位/接口系统以ASIC测试数据串行扫描，然后将ASIC测试数据馈送到ASIC，然后从ASIC接收ASIC响应数据，然后串行扫描ASIC响应数据。
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