发明申请
US20130320450A1 MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS
有权
使用硅氧烷封装，早期黑曜石和延伸植入的28 NM低功率/高性能技术的PMOS器件的中间现场拨号信号连接
- 专利标题： MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS
- 专利标题（中）： 使用硅氧烷封装，早期黑曜石和延伸植入的28 NM低功率/高性能技术的PMOS器件的中间现场拨号信号连接
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申请号： US13482410申请日： 2012-05-29
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公开(公告)号： US20130320450A1公开(公告)日： 2013-12-05
- 发明人: Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
- 申请人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
- 申请人地址： SG Singapore
- 专利权人： GlobalFoundries
- 当前专利权人： GlobalFoundries
- 当前专利权人地址： SG Singapore
- 主分类号： H01L27/088
- IPC分类号： H01L27/088 ; H01L21/8238 ; H01L21/336
摘要：
A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
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