Invention Application
US20140015093A1 CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD
有权
SOI基底技术和方法中MIM元件的充电破坏避免
- Patent Title: CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD
- Patent Title (中): SOI基底技术和方法中MIM元件的充电破坏避免
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Application No.: US14030414Application Date: 2013-09-18
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Publication No.: US20140015093A1Publication Date: 2014-01-16
- Inventor: William F. CLARK, JR. , Stephen E. LUCE
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Main IPC: H01L49/02
- IPC: H01L49/02
Abstract:
A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.
Public/Granted literature
- US09059131B2 Charge breakdown avoidance for MIM elements in SOI base technology and method Public/Granted day:2015-06-16
Information query
IPC分类:
