发明申请
- 专利标题: VLSI Circuit Verification
- 专利标题(中): VLSI电路验证
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申请号: US14116776申请日: 2012-05-24
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公开(公告)号: US20140088911A1公开(公告)日: 2014-03-27
- 发明人: Avi Rabinovich , Nadav Cohen , Gilad Cohen , Genady Okrain , Aviad Levy
- 申请人: Avi Rabinovich , Nadav Cohen , Gilad Cohen , Genady Okrain , Aviad Levy
- 申请人地址: IL Yokneam
- 专利权人: CIGOL DIGITAL SYSTEMS LTD.
- 当前专利权人: CIGOL DIGITAL SYSTEMS LTD.
- 当前专利权人地址: IL Yokneam
- 国际申请: PCT/IB12/52604 WO 20120524
- 主分类号: G01R31/28
- IPC分类号: G01R31/28
摘要:
A method of connecting to an integrated circuit. A target integrated circuit (102) is provided with an embedded agent (104) for exporting signals. While the target integrated circuit (102) is operating, data signals from one or more collection points (252) in the integrated circuit (102) are collected by the embedded agent (104), at least at a clock rate of operation of the integrated circuit at the one or more collection points (252), in parallel to the target circuit (102) operation. The collected data signals are inserted into packets, by the embedded agent (104) and the packets are transmitted to a unit external to the integrated circuit, in real time.
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