Invention Application
US20140149726A1 ESTABLISHING A BRANCH TARGET INSTRUCTION CACHE (BTIC) ENTRY FOR SUBROUTINE RETURNS TO REDUCE EXECUTION PIPELINE BUBBLES, AND RELATED SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA
有权
建立分支目标指导缓存(BTIC)进入SUBRONTINE返回以减少执行管道泡沫以及相关系统,方法和计算机可读介质
- Patent Title: ESTABLISHING A BRANCH TARGET INSTRUCTION CACHE (BTIC) ENTRY FOR SUBROUTINE RETURNS TO REDUCE EXECUTION PIPELINE BUBBLES, AND RELATED SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA
- Patent Title (中): 建立分支目标指导缓存(BTIC)进入SUBRONTINE返回以减少执行管道泡沫以及相关系统,方法和计算机可读介质
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Application No.: US13792335Application Date: 2013-03-11
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Publication No.: US20140149726A1Publication Date: 2014-05-29
- Inventor: James Norris Dieffenderfer , Michael William Morrow , Michael Scott McIlvaine , Daren Eugene Streett , Vimal K. Reddy , Brian Michael Stempel
- Applicant: QUALCOMM INCORPORATED
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Main IPC: G06F9/38
- IPC: G06F9/38

Abstract:
Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.
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