公开(公告)号：US20130290683A1

公开(公告)日：2013-10-31

申请号：US13655622

申请日：2012-10-19

Applicant: QUALCOMM INCORPORATED

Inventor： Melinda J. Brown ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Brian Michael Stempel ,  Michael Scott McIlvaine

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30018 ,  G06F9/3838

Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. in this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中消除冗余掩蔽操作。 在一个实施例中，由指令处理电路检测指示将值写入第一寄存器的操作的指令流中的第一指令，该值具有小于第一寄存器的大小的值。 电路还检测指示流中指示在第一寄存器上的屏蔽操作的第二指令。 在确定掩蔽操作指示对第一寄存器的读取操作和写入操作并且具有等于或大于值大小的身份掩码大小的情况下，屏蔽操作被消除。 以这种方式，消除掩蔽操作避免了潜在的写后危害，并且通过从执行流水线中移除冗余操作来提高CPU的性能。

公开(公告)号：US20170046167A1

公开(公告)日：2017-02-16

申请号：US14863612

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Luke Yen ,  Michael William Morrow ,  Jeffery Michael Schottmiller ,  James Norris Dieffenderfer

IPC: G06F9/38 ,  G06F9/30

Abstract: Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT) are disclosed. In one aspect, an instruction processing circuit accesses a PAT containing entries each comprising an address of a memory instruction. Upon detecting a memory instruction in an instruction stream, the instruction processing circuit determines whether the PAT contains an entry having an address of the memory instruction. If so, the instruction processing circuit prevents the detected memory instruction from taking effect before at least one pending memory instruction older than the detected memory instruction, to preempt a memory instruction punt. In some aspects, the instruction processing circuit may determine, upon execution of a pending memory instruction, whether a hazard associated with the detected memory instruction has occurred. If so, an entry for the detected memory instruction is generated in the PAT.

Abstract translation: 公开了使用平底逃避表（PAT）预测计算机处理器中的存储器指令平移。 在一个方面，指令处理电路访问包含条目的PAT，每个条目包括存储器指令的地址。 在检测到指令流中的存储器指令时，指令处理电路确定PAT是否包含具有存储器指令地址的条目。 如果是这样，则指令处理电路防止检测到的存储器指令在比检测到的存储器指令之前的至少一个未决存储器指令之前生效，以抢占存储器指令punt。 在一些方面，指令处理电路可以在执行待决存储器指令时确定是否已经发生与检测到的存储器指令相关联的危险。 如果是，则在PAT中生成检测到的存储器指令的条目。

公开(公告)号：US09477476B2

公开(公告)日：2016-10-25

申请号：US13686229

申请日：2012-11-27

Applicant: QUALCOMM Incorporated

Inventor： Melinda J. Brown ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Brian Michael Stempel ,  Michael Scott McIlvaine ,  Rodney Wayne Smith ,  Jeffrey M. Schottmiller ,  Andrew S. Irwin

IPC: G06F9/00 ,  G06F9/44 ,  G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30167

Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register. In this manner, conversion of multiple instructions for generating a constant into the fused instruction(s) removes the potential for a read-after-write hazard and associated consequences caused by dependencies between certain instructions, while reducing a number of clock cycles required to process the instructions.

Abstract translation: 公开了立即值的融合，指令处理电路中的基于写入的指令以及相关的处理器系统，方法和计算机可读介质。 在一个实施例中，指令处理电路检测指示向寄存器写入立即值的操作的第一指令。 电路还检测至少一个后续指令，指示在保持寄存器的第二部分的值的同时重写寄存器的至少一个第一部分的操作。 所述至少一个后续指令被转换（或替代）与一个融合指令，其指示写入寄存器的至少一个第一部分和第二部分的操作。 以这种方式，将用于产生常数的多个指令转换为融合指令消除了读写后危险和由特定指令之间的依赖性引起的相关后果的可能性，同时减少了处理所需的时钟周期数 说明。

公开(公告)号：US20140281439A1

公开(公告)日：2014-09-18

申请号：US13832119

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Vimal K. Reddy ,  Niket K. Choudhary ,  Michael William Morrow

IPC: G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30069 ,  G06F9/30145 ,  G06F9/3017

Abstract: Methods and apparatuses for optimizing hard-to-predict short forward branches. A method detects a forward conditional branch with at least one instruction between the forward conditional branch and forward conditional branch target. The method determines whether a first of the at least one instruction includes at least one of a conditional branch or a condition-code setter. If the first instruction does not have the at least one of a conditional branch or a condition-code setter, the first instruction is dynamically assigned an inverted condition to optimize a code path. The method determines if there is a next instruction between the forward conditional branch and its target. If there is, the method analyzes the next instruction. If there is no next instruction, the method executes the optimized code path. If the instruction includes the conditional branch or condition-code setter, it discards dynamic assignments and executes the detected forward conditional branch.

Abstract translation: 优化难以预测的短期分支的方法和装置。 一种方法使用前向条件分支和前向条件分支目标之间的至少一条指令检测前向条件分支。 该方法确定至少一个指令中的第一个是否包括条件分支或条件码设置器中的至少一个。 如果第一指令不具有条件分支或条件码设置器中的至少一个，则第一指令被动态地分配反转条件以优化代码路径。 该方法确定在前向条件分支与其目标之间是否存在下一条指令。 如果有，则该方法分析下一条指令。 如果没有下一条指令，则该方法执行优化的代码路径。 如果指令包括条件分支或条件代码设置器，它将丢弃动态分配并执行检测到的前向条件分支。

公开(公告)号：US20140281391A1

公开(公告)日：2014-09-18

申请号：US13827867

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： James Norris Dieffenderfer ,  Michael William Morrow ,  Rodney Wayne Smith ,  Jeffery M. Schottmiller ,  Daniel S. Higdon ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Kulin N. Kothari

IPC: G06F9/30

Abstract: A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache includes a field to indicate whether its stored constant value is valid, and a field to associate the entry with an architected register. Once a constant value is stored in the cache, it is immediately available for forwarding to a processor pipeline where a decoded instruction may need the constant value as an operand.

Abstract translation: 解码将立即数移动（复制或写入）到结构化寄存器的移动即时指令时，在缓存中存储恒定值（立即数或立即数）的处理器。 常量值存储在缓存中的条目中。 缓存中的每个条目包括一个字段，用于指示其存储的常量值是否有效，以及一个字段，用于将条目与架构化寄存器相关联。 一旦常数值被存储在高速缓存中，则立即可以转发到处理器流水线，其中解码的指令可能需要常数值作为操作数。

公开(公告)号：US20140047221A1

公开(公告)日：2014-02-13

申请号：US13788008

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew S. Irwin ,  James Norris Dieffenderfer ,  Melinda J. Brown ,  Jeffery M. Schottmiller ,  Brian Michael Stempel ,  Michael Scott McIlvaine ,  Rodney Wayne Smith ,  Michael William Morrow

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30072

Abstract: Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also detects a flag-consuming instruction in the instruction stream indicating a second operation consuming the first flag result as an input. The instruction processing circuit generates a fused instruction indicating the first operation generating the first flag result and indicating the second operation consuming the first flag result as the input. In this manner, as a non-limiting example, the fused instruction eliminates a potential for a read-after-write hazard between the flag-producing instruction and the flag-consuming instruction.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中对产生标记和标记消息的指令进行融合。 在一个实施例中，指令处理电路在指令流中检测指示产生第一标志结果的第一操作的标志产生指令。 指令处理电路还检测指示流中指示消耗第一标志结果的第二操作的指令消息指令作为输入。 指令处理电路产生指示第一操作的融合指令，该第一操作产生第一标志结果并指示第二操作消耗第一标志结果作为输入。 以这种方式，作为非限制性示例，融合指令消除了标志产生指令和标志消耗指令之间的写后读取危险的可能性。

公开(公告)号：US20130311754A1

公开(公告)日：2013-11-21

申请号：US13676146

申请日：2012-11-14

Applicant: QUALCOMM INCORPORATED

Inventor： Melinda J. Brown ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Rodney Wayne Smith ,  Jeffrey M. Schottmiller ,  Andrew S. Irwin ,  Michael William Morrow

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3017

Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中具有相反条件的条件写指令。 在一个实施例中，由指令处理电路检测基于评估第一条件将第一值写入目标寄存器的第一条件写入指令。 该电路还基于评估与第一条件逻辑相反的第二条件，检测向目标寄存器写入第二值的第二条件写入指令。 选择第一个条件或第二个条件作为融合指令条件，并将相应的值选为if-true和if-false值。 如果融合指令条件评估为真，则生成融合指令，以便如果融合指令条件评估为真，则将if-true值有选择地写入目标寄存器，如果融合指令条件评估为false，则选择性地将if-false值写入目标寄存器。

公开(公告)号：US20160092232A1

公开(公告)日：2016-03-31

申请号：US14498508

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Michael William Morrow

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3832

Abstract: Propagating constant values using a computed constants table, and related apparatuses and methods are disclosed. In one aspect, an apparatus comprises an instruction processing circuit configured to provide a computed constants table containing one or more entries. Each entry of the computed constants table comprises an attribute and a computed constant value. The instruction processing circuit is configured to detect a deterministic instruction in an instruction stream. Upon detecting the deterministic instruction, the instruction processing circuit determines whether an attribute of the deterministic instruction matches an entry of the computed constants table. If so, the instruction processing circuit provides the computed constant value stored in the entry to at least one dependent instruction. In this manner, a computed constant value may be propagated between instructions without requiring the deterministic instruction to be re-executed.

Abstract translation: 公开了使用计算常数表传播常数值，以及相关装置和方法。 一方面，一种装置包括：指令处理电路，被配置为提供包含一个或多个条目的计算常数表。 计算的常数表的每个条目包括属性和计算的常数值。 指令处理电路被配置为检测指令流中的确定性指令。 在检测到确定性指令时，指令处理电路确定确定性指令的属性是否与所计算的常数表的条目匹配。 如果是，则指令处理电路将存储在条目中的计算的常数值提供给至少一个依赖指令。 以这种方式，计算的常数值可以在指令之间传播，而不需要重新执行确定性指令。

公开(公告)号：US09514061B1

公开(公告)日：2016-12-06

申请号：US14716947

申请日：2015-05-20

Applicant: QUALCOMM Incorporated

Inventor： Henry Arthur Pellerin, III ,  Thomas Philip Speier ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine

IPC: G06F12/00 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract translation: 存储器结构使用索引标签压缩结构压缩存储器标签的一部分。 存储器标签的一组较高位可以存储在索引标签压缩结构中，其中较高位的集合由索引值标识。 标签阵列存储存储器标签的一组较低位，以及标识在存储标签的较高位的集合的标签压缩结构中的条目的索引值。 存储器标签可以包括存储在数据阵列中的数据元素的存储器地址的至少一部分。

公开(公告)号：US09317293B2

公开(公告)日：2016-04-19

申请号：US13792335

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： James Norris Dieffenderfer ,  Michael William Morrow ,  Michael Scott McIlvaine ,  Daren Eugene Streett ,  Vimal K. Reddy ,  Brian Michael Stempel

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3808 ,  G06F9/30054

Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.

Abstract translation: 建立用于子程序的分支目标指令缓存（BTIC）条目返回以减少管道气泡，以及相关系统，方法和计算机可读介质。 在一个实施例中，建立BTIC条目的方法包括检测执行流水线中的子程序调用。 作为响应，在子程序返回的BTIC条目中写入与子程序调用顺序取得的至少一个指令作为分支目标指令。 计算下一个指令提取地址，并将其写入BTIC条目中的下一个指令获取地址字段。 以这种方式，即使第一次遇到子程序返回或从不同的呼叫位置调用子程序，BTIC可以为子程序返回提供正确的分支目标指令和下一个指令获取地址数据。