Invention Application
- Patent Title: SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME
- Patent Title (中): SIC外延波形及其制造方法
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Application No.: US14240662Application Date: 2012-09-04
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Publication No.: US20140175461A1Publication Date: 2014-06-26
- Inventor: Kenji Momose , Michiya Odawara , Daisuke Muto , Yoshiaki Kageshima
- Applicant: Kenji Momose , Michiya Odawara , Daisuke Muto , Yoshiaki Kageshima
- Applicant Address: JP Minato-ku, Tokyo
- Assignee: SHOWA DENKO K.K.
- Current Assignee: SHOWA DENKO K.K.
- Current Assignee Address: JP Minato-ku, Tokyo
- Priority: JP2011-197626 20110909
- International Application: PCT/JP2012/072454 WO 20120904
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/16

Abstract:
Provided are a SiC epitaxial wafer in which the surface density of stacking faults is reduced, and a manufacturing method thereof. The method for manufacturing such a SiC epitaxial wafer comprises a step of determining a ratio of basal plane dislocations (BPD), which causes stacking faults in a SiC epitaxial film of a prescribed thickness which is formed on a SiC single crystal substrate having an off angle, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, a step of determining an upper limit of surface density of basal plane dislocations on the growth surface of a SiC single crystal substrate used based on the above ratio, and a step of preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio.
Public/Granted literature
- US09287121B2 SIC epitaxial wafer and method for manufacturing same Public/Granted day:2016-03-15
Information query
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