Invention Application
US20140201405A1 INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES
有权
使用封装输入/输出接口的封装中的多个插座的互连
- Patent Title: INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES
- Patent Title (中): 使用封装输入/输出接口的封装中的多个插座的互连
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Application No.: US13996107Application Date: 2011-12-22
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Publication No.: US20140201405A1Publication Date: 2014-07-17
- Inventor: Thomas P. Thomas , Randy B. Osborne , Rajesh Kumar
- Applicant: Thomas P. Thomas , Randy B. Osborne , Rajesh Kumar
- International Application: PCT/US11/66976 WO 20111222
- Main IPC: G06F13/364
- IPC: G06F13/364 ; G06F13/16 ; G06F3/0488
Abstract:
An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched.
Public/Granted literature
- US09535865B2 Interconnection of multiple chips in a package Public/Granted day:2017-01-03
Information query
