Invention Application
- Patent Title: SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES
- Patent Title (中): 半导体器件的封装和封装方法
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Application No.: US14257013Application Date: 2014-04-21
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Publication No.: US20140225242A1Publication Date: 2014-08-14
- Inventor: Chin Hock TOH , Kriangsak Sae LE
- Applicant: United Test and Assembly Center Ltd.
- Applicant Address: SG Singapore
- Assignee: United Test and Assembly Center Ltd.
- Current Assignee: United Test and Assembly Center Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/00

Abstract:
A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.
Public/Granted literature
- US09117808B2 Semiconductor packages and methods of packaging semiconductor devices Public/Granted day:2015-08-25
Information query
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