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公开(公告)号：US09960130B2
公开(公告)日：2018-05-01
申请号：US14615436
申请日：2015-02-06
CPC分类号： H01L24/05 , H01L23/3171 , H01L24/03 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L2224/04042 , H01L2224/05017 , H01L2224/05124 , H01L2224/05147 , H01L2224/0519 , H01L2224/0529 , H01L2224/05393 , H01L2224/05552 , H01L2224/05558 , H01L2224/05618 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/2919 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45164 , H01L2224/48227 , H01L2224/48453 , H01L2224/48465 , H01L2224/48507 , H01L2224/73265 , H01L2924/00014 , H01L2924/013 , H01L2924/01029 , H01L2924/00
摘要： Devices and methods for forming a device are disclosed. The device includes a contact region disposed over a last interconnect level of the device. The device includes a final passivation layer having at least an opening which at least partially exposes a top surface of the contact region and a buffer layer disposed at least over a first exposed portion of the top surface of the contact region. When an electrically conductive interconnection couples to the contact region, the buffer layer absorbs a portion of a force exerted to form an interconnection between the electrically conductive interconnection and the contact region.
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公开(公告)号：US09613877B2
公开(公告)日：2017-04-04
申请号：US14051417
申请日：2013-10-10
IPC分类号： H01L23/495 , H01L21/02 , H01L29/84 , H01L23/04 , H01L23/00
CPC分类号： H01L23/04 , B81B7/007 , B81B2207/07 , H01L23/053 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L24/92 , H01L2224/2919 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48105 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/8592 , H01L2224/92247 , H01L2924/10158 , H01L2924/1461 , H01L2924/15311 , H01L2924/16151 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.
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公开(公告)号：US20160211196A1
公开(公告)日：2016-07-21
申请号：US15007607
申请日：2016-01-27
IPC分类号： H01L23/495 , H01L23/31
CPC分类号： H01L23/49506 , H01L21/4832 , H01L23/3107 , H01L23/3157 , H01L23/495 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32245 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48639 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/85439 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , Y10T29/49121 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.
摘要翻译： 制造引线框架的方法包括提供在顶表面具有多个孔的导电层。 多个孔在导电层上形成引线和管芯焊盘的结构。 多个孔填充有非导电材料。 下一个; 导电箔附着在导电层和非导电环氧材料的顶表面上。 导电箔被蚀刻以形成引线网络，管芯焊盘，总线，坝条和连接线，其中总线将引线连接到堤坝，坝条连接到连接线， 连接线连接到管芯焊盘。
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公开(公告)号：US09391026B2
公开(公告)日：2016-07-12
申请号：US14561157
申请日：2014-12-04
发明人： Chuen Khiang Wang
IPC分类号： H01L23/31 , H01L23/498 , H01L23/538 , H01L21/56 , H01L21/48 , H01L23/28 , H05K1/09 , H05K1/11
CPC分类号： H01L23/5384 , H01L21/4832 , H01L21/56 , H01L21/568 , H01L23/28 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49866 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H05K1/09 , H05K1/115 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.
摘要翻译： 提供封装衬底，半导体封装以及用于形成半导体封装的方法。 封装衬底包括具有第一和第二主表面的基底衬底和延伸穿过基底衬底的第一至第二主表面的多个通孔触头。 具有多个开口的第一导电层设置在基底基板的第一表面上并经由触点。 开口被配置成匹配封装衬底的导电迹线布局。 导电迹线设置在第一导电层上。 导电迹线通过第一导电层的一些开口直接耦合到通孔触点。
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公开(公告)号：US09142487B2
公开(公告)日：2015-09-22
申请号：US13737923
申请日：2013-01-09
IPC分类号： H01L23/48 , H01L23/52 , H01L25/065 , H01L21/683 , H01L23/498 , H01L23/538 , H01L23/00 , H01L25/10 , H01L21/50 , H01L21/56
CPC分类号： H01L21/568 , H01L21/50 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/78 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5389 , H01L24/03 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68345 , H01L2224/0231 , H01L2224/0237 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/24227 , H01L2224/2518 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/01029 , H01L2924/01033 , H01L2924/01087 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.
摘要翻译： 公开了一种用于半导体封装的结构件。 结构构件包括多个封装区域，以便于例如晶片格式的封装模具。 包装区域具有由周边区域包围的管芯附着区域。 裸片附接到芯片附接区域。 一方面，管芯附着区域通过用于容纳管芯的结构构件的表面开口。 通孔设置在周边区域。 结构构件减少在封装模具中使用的模具化合物的固化期间可能发生的翘曲。 在另一方面，管芯附着区域不具有开口。 在这种情况下，结构件用作管芯和衬底之间的插入件。
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公开(公告)号：US20150214187A1
公开(公告)日：2015-07-30
申请号：US14678840
申请日：2015-04-03
IPC分类号： H01L23/00 , H01L21/56 , H01L23/495 , H01L23/528 , H01L23/532 , H01L21/78 , H01L21/768
CPC分类号： H01L24/97 , H01L21/2855 , H01L21/4821 , H01L21/50 , H01L21/56 , H01L21/568 , H01L21/76802 , H01L21/76879 , H01L21/78 , H01L23/3107 , H01L23/495 , H01L23/49541 , H01L23/528 , H01L23/53228 , H01L24/48 , H01L24/81 , H01L24/85 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2224/81801 , H01L2224/85801 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.
摘要翻译： 本发明的实施例涉及用于制造I / O触点的区域阵列的引线框区阵列封装技术。 制造的封装包括聚合物材料基板，位于聚合物材料基板顶部的互连层，通过引线接合或导电柱连接到互连层的管芯，以及封装管芯，互连层和引线接合的模制化合物 或导电支柱。 聚合物材料通常在组装之前形成在载体上，并且不被去除以用作制造的包装的基材。 聚合物材料基板具有多个通孔，其在预定位置处暴露互连层，并使得焊球安装或焊接印刷直接连接到互连层。 在一些实施例中，半导体封装在聚合物材料衬底中包括释放沟道，以改善制造的封装的可靠性。
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公开(公告)号：US20150061101A1
公开(公告)日：2015-03-05
申请号：US14521481
申请日：2014-10-23
发明人： Kriangsak Sae LE , Chee Kay CHOW
IPC分类号： H01L25/065 , H01L23/31 , H01L23/00 , H01L21/56 , H01L25/00 , H01L23/495
CPC分类号： H01L25/0655 , H01L21/561 , H01L21/563 , H01L23/147 , H01L23/3128 , H01L23/3135 , H01L23/49503 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/06135 , H01L2224/06181 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/1703 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/814 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81815 , H01L2224/8191 , H01L2224/83102 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06548 , H01L2225/06555 , H01L2225/06568 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15165 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2224/83
摘要： A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer.
摘要翻译： 公开了一种形成半导体组件的方法。 该方法包括通过插入器通孔提供插入器。 插入器包括第一和第二表面。 通过插入件通孔从插入件的第一表面延伸到第二表面。 具有通过插入器通孔的插入件使得具有非常细的接触间距的管芯与具有相对较大接触间距的外部器件的连接和电耦合。 至少第一管芯安装在插入件的第一表面上的至少一个管芯附着区域上。 第一裸片包括其上具有第一导电接触的第一表面。 中间层包括具有与第一裸片相同的CTE的材料。 第一管芯的第一导电接触件连接到插入件的第一表面上的通孔插入件通孔。 执行不需要回流处理的接合工艺，以形成第一管芯和插入件之间的连接。
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公开(公告)号：US20140225242A1
公开(公告)日：2014-08-14
申请号：US14257013
申请日：2014-04-21
发明人： Chin Hock TOH , Kriangsak Sae LE
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/49503 , H01L21/561 , H01L21/563 , H01L23/147 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/06 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/89 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/06135 , H01L2224/131 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/814 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81815 , H01L2224/8191 , H01L2224/83102 , H01L2224/92125 , H01L2224/97 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15165 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/00014
摘要： A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.
摘要翻译： 公开了一种形成半导体组件的方法。 该方法包括通过插入器通孔提供插入器。 插入件包括第一表面和第二表面。 通过插入件通孔从插入件的第一表面延伸到第二表面。 第一管芯安装在插入件的第一表面上。 第一裸片包括其上具有第一导电接触的第一表面。 插入件包括与第一模具类似的具有热膨胀系数（CTE）的材料。 第一管芯的第一导电接触件连接到插入件的第一表面上的通孔插入件通孔。
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公开(公告)号：US09842792B2
公开(公告)日：2017-12-12
申请号：US15007607
申请日：2016-01-27
IPC分类号： H01L23/495 , H01L21/48 , H01L23/31 , H01L23/00
CPC分类号： H01L23/49506 , H01L21/4832 , H01L23/3107 , H01L23/3157 , H01L23/495 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32245 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48639 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/85439 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , Y10T29/49121 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.
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公开(公告)号：US09136142B2
公开(公告)日：2015-09-15
申请号：US14257017
申请日：2014-04-21
发明人： Chuen Khiang Wang , Nathapong Suthiwongsunthorn , Kriangsak Sae Le , Antonio Jr B Dimaano , Catherine Bee Liang Ng , Richard Te Gan , Kian Teng Eng
IPC分类号： H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495 , H01L23/498 , H01L25/03 , H01L25/10 , H01L25/16 , H01L23/36 , H01L23/48 , H01L23/00
CPC分类号： H01L23/49861 , H01L21/2885 , H01L21/4825 , H01L21/4828 , H01L21/4832 , H01L21/4839 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3121 , H01L23/36 , H01L23/481 , H01L23/49503 , H01L23/4952 , H01L23/49534 , H01L23/49537 , H01L23/49541 , H01L23/49575 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/9211 , H01L2224/92125 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06548 , H01L2225/06558 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
摘要翻译： 公开了一种设备。 该装置包括具有第一和第二主表面的载体衬底。 第一表面包括管芯区域和接触焊盘，第二表面包括封装接触。 载体衬底包括图案化引线框架，其将导电迹线和具有通孔触点的通孔级限定在线路电平。 图案化引线框架提供接触焊盘和封装触点之间的互连。 载体衬底还包括隔离导电迹线和通孔触点的电介质层。 该装置包括安装在第一表面的管芯区域上的管芯。
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