The present technique relates to an image processing device and method capable of performing an encoding process or a decoding process on an image at high speed. Similarly, arithmetic coding parameters arranged together in the syntax are subjected to a variable length (fixed length) decoding process together. Similarly, arithmetic coding parameters arranged together in the syntax are subjected to an arithmetic decoding process together. Accordingly, since the alternations of firmware and hardware are performed together, it is possible to improve the processing efficiency of decoding. As a result, it is possible to perform the process at high speed. The present disclosure can be applied to image processing devices, for example.