Invention Application
- Patent Title: IMPLEMENTING ECC REDUNDANCY USING RECONFIGURABLE LOGIC BLOCKS
- Patent Title (中): 使用可重构逻辑块实现ECC冗余
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Application No.: US13867207Application Date: 2013-04-22
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Publication No.: US20140317473A1Publication Date: 2014-10-23
- Inventor: Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: G11C29/08
- IPC: G11C29/08

Abstract:
A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.
Public/Granted literature
- US09230687B2 Implementing ECC redundancy using reconfigurable logic blocks Public/Granted day:2016-01-05
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